Writing Synthesizable VHDL Code for FPGAs

2013 ◽  
pp. 147-155
Author(s):  
Eduardo Augusto Bezerra ◽  
Djones Vinicius Lettnin
Keyword(s):  
Vhdl Code

DESAIN DAN SIMULASI PERANGKAT KERAS MULTIOPERAND MSB-FIRST ADDER BILANGAN BERTANDA MENGGUNAKAN VHDL

e-NARODROID ◽  
2015 ◽  
Vol 1 (1) ◽  
Author(s):  
Arief Budijanto
Keyword(s):  
Intermediate Result ◽  
Msb First ◽  
Vhdl Code

Msb-First Adder merupakan metode penjumlahan bilangan bulat yang dilakukan mulai dari bobot bit yang paling signifikan terlebih dahulu atau dari bit paling kiri menuju kekanan. Metode pemjumlahan ini mempunyai kelebihan jika proses penjumlahan dibatasi oleh waktu (deadline), karena yang dijumlahkan terlebih dahulu adalah bit yang mempunyai bobot paling signifikan. Selain itu metoda ini juga menunjukan kinerja yang lebih baik ketika digunakan untuk menjumlahkan bilangan banyak (multioperand). Dalam penelitian ini dibuat suatu arsitektur MSB-First Adder yang diaplikasikan untuk komputasi Transformasi Fourier Diskrit (TFD). Tahapan yang dilakukan dalam peneltian ini adalah desain diagram blok arsitektur MSB-First Adder dan Arsitektur TFD yang menggunakan MSBFirst Adder, kemudian memodelkan dalam bentuk VHDL Code . Tahapan yang terakhir yaitu melakukan verifikasi dan analisis dari hasil komputasi TFD yang menggunakan MSB-First adder dibandingkan dengan TFD menggunakan LSB-First Adder dan MATLAB. Hasil akhir komputasi TFD Multioperand MSB-First dengan TFD LSB-First memperlihatkan hasil yang sama. Selain itu pada komputasi TFD Multioperand MSB-First tersedianya hasil-antara (intermediate-result) pada awal proses yang mendekati hasil akhirnya. Hasil ini tidak terjadi pada komputasi prosesor DFT LSB-First. Waktu yang dibutuhkan untuk proses komputasi TFD Multioperand MSB-First adalah 158,506 µS, sedangkan TFD LSB-First adalah 55,308 µS. Agar waktu komputasi TFD Multioperand MSB-First akan mendekati sama dengan waktu komputasi TFD LSB-First, jika pada bagian output memory (RAM dan ROM) dirubah menjadi 16 saluran output (tiap saluran 16 bit) dan multiply nya disusun paralel sebanyak 16 buah.Kata kunci: MSB-First Adder, LSB-First Adder, Hasil-Antara, VHDL, TFD

scholarly journals Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1589
Author(s):  
Krzysztof Kołek ◽  
Andrzej Firlit ◽  
Krzysztof Piątek ◽  
Krzysztof Chmielowiec
Keyword(s):  
Code Generation ◽  
State Of The Art ◽  
Power Grids ◽  
Practical Implementation ◽  
System A ◽  
Measuring Devices ◽  
Point Representation ◽  
Measurement Algorithm ◽  
On Chip ◽  
Vhdl Code

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

I-DMAC: An Intelligent DMA Controller for Utilization - Aware Video Streaming used in AI Applications

2021 ◽  
pp. 60-70
Author(s):  
Piyush Kumar Shukla ◽  
◽  
Prashant Kumar Shukla ◽  
Keyword(s):  
Video Processing ◽  
High Performance ◽  
Data Transfer ◽  
Direct Memory Access ◽  
Large Data ◽  
Video Frame ◽  
Microprocessor System ◽  
Bulk Data ◽  
Xilinx Fpga ◽  
Vhdl Code

The interpretation of large data streams necessitates high-performance repeated transfers, which overload Microprocessor System on Chips (SoC). The effective direct memory access (DMA) controller performs bulk data transfers without the CPU's involvement. The Direct Memory Controller (DMAC) solves this by facilitating bulk data transfer and execution. In this work, we created an intelligent DMAC (I-DMAC) for accessing video processing data without using CPUs. The model includes Bus selection Module, User control signal, Status Register, DMA supported Address, and AXI-PCI subsystems for improved video frame analysis. These modules are experimentally verified in Xilinx FPGA SoC architecture using VHDL code simulation and results compared to the E-DMAC model.

Chopper-controlled PMDC motor drive using VHDL code

2009 ◽  
Author(s):  
Marcelo F. Castoldi ◽  
Gabriel R. C. Dias ◽  
Manoel L. Aguiar ◽  
Valentin O. Roda
Keyword(s):  
Motor Drive ◽  
Vhdl Code

An Optimized FPGA Implementation of CAN 2.0 Protocol Error Detection Circuitry

2017 ◽  
Vol 6 (3) ◽  
pp. 602
Author(s):  
Md Farukh Hashmi ◽  
Avinash G. Keskar
Keyword(s):  
Embedded System ◽  
Data Storage ◽  
Error Detection ◽  
Low Cost ◽  
Disk Drive ◽  
Critical Issue ◽  
Subsequent Treatment ◽  
Area Network ◽  
Reconfigurable Platform ◽  
Vhdl Code

Controller Area Network is an ideal serial bus design suitable for modern embedded system based networks. It finds its use in most of critical applications, where error detection and subsequent treatment on error is a critical issue. CRC (Cyclic Redundancy Check) block was developed on FPGA in order to meet the needs for simple, low power and low cost wireless communication. This paper gives a short overview of CRC block in the Digital transmitter based on the CAN 2.0 protocols. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. This technique is also sometimes applied to data storage devices, such as a disk drive. In this paper a technique to model the error detection circuitry of CAN 2.0 protocols on reconfigurable platform have been discussed? The software simulation results are presented in the form of timing diagram.FPGA implementation results shows that the circuitry requires very small amount of digital hardware. The Purpose of the research is to diversify the design methods by using VHDL code entry through Modelsim 5.5e simulator and Xilinx ISE8.3i.The VHDL code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Sparten3 FPGA .Here, Simulation and Synthesized results are also presented to verify the functionality of the CRC -16 Block. The data rate of CRC block is 250 kbps .Estimated power consumption and maximum operating frequency of the circuitry is also provided.

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