Super Resolution for Multimedia, Image, and Video Processing Applications

Author(s):  
K. Malczewski ◽  
R. Stasiński
Author(s):  
Md Mamunur Rashid

Image Processing in Multimedia Applications treats a number of critical topics in multimedia systems, with respect to image and video processing techniques and their implementations. These techniques include the Image and video compression techniques and standards, and Image and video indexing and retrieval techniques. Image Processing is an important tool to develop a Multimedia system design.


2004 ◽  
Vol 6 (4) ◽  
pp. 539-552 ◽  
Author(s):  
R. Cucchiara ◽  
M. Piccardi ◽  
A. Prati

2018 ◽  
Vol 1 (2) ◽  
pp. 17-23
Author(s):  
Takialddin Al Smadi

This survey outlines the use of computer vision in Image and video processing in multidisciplinary applications; either in academia or industry, which are active in this field.The scope of this paper covers the theoretical and practical aspects in image and video processing in addition of computer vision, from essential research to evolution of application.In this paper a various subjects of image processing and computer vision will be demonstrated ,these subjects are spanned from the evolution of mobile augmented reality (MAR) applications, to augmented reality under 3D modeling and real time depth imaging, video processing algorithms will be discussed to get higher depth video compression, beside that in the field of mobile platform an automatic computer vision system for citrus fruit has been implemented ,where the Bayesian classification with Boundary Growing to detect the text in the video scene. Also the paper illustrates the usability of the handed interactive method to the portable projector based on augmented reality.   © 2018 JASET, International Scholars and Researchers Association


Author(s):  
Chamin Morikawa ◽  
Michihiro Kobayashi ◽  
Masaki Satoh ◽  
Yasuhiro Kuroda ◽  
Teppei Inomata ◽  
...  

2016 ◽  
Vol 26 (04) ◽  
pp. 1750054
Author(s):  
M. Kiruba ◽  
V. Sumathy

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.


2020 ◽  
pp. 147-161
Author(s):  
Ashwin Pajankar ◽  
Sharvani Chandu

2000 ◽  
Vol 80 (11) ◽  
pp. 2323-2336 ◽  
Author(s):  
Klaus Illgner

Author(s):  
Alla Levina ◽  
Sergey Taranov

Theory of wavelet transform is a powerful tool for image and video processing. Mathematical concepts of wavelet transform and filter bank have been studied carefully in many works. This work presents application of new construction of linear and robust codes based on wavelet decomposition and its application in ADV612 chips. We present the model of the error-coding scheme that allows to detect errors in the ADV612 chips with high probability. In our work, we will show that developed and presented scheme of protection drastically improves the resistance of ADV612 chips to malfunctions and errors.


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