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Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
Latest Publications
TOTAL DOCUMENTS
17
(FIVE YEARS 0)
H-INDEX
2
(FIVE YEARS 0)
Published By Springer Netherlands
9789048193783, 9789048193790
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Latest Documents
Most Cited Documents
Contributed Authors
Related Sources
Related Keywords
How Does Inverse Temperature Dependence Affect Timing Sign-Off
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_13
◽
2010
◽
pp. 179-189
◽
Cited By ~ 2
Author(s):
Sean H. Wu
◽
Alexander Tetelbaum
◽
Li-C. Wang
Keyword(s):
Temperature Dependence
◽
Inverse Temperature
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DC–DC Converter Technologies for On-Chip Distributed Power Supply Systems – 3D Stacking and Hybrid Operation
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_16
◽
2010
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pp. 221-247
Author(s):
Makoto Takamiya
◽
Koichi Onizuka
◽
Koichi Ishida
◽
Takayasu Sakurai
Keyword(s):
Power Supply
◽
Distributed Power
◽
Hybrid Operation
◽
On Chip
◽
3D Stacking
◽
Supply Systems
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Process Variability-Induced Timing Failures – A Challenge in Nanometer CMOS Low-Power Design
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_12
◽
2010
◽
pp. 163-177
◽
Cited By ~ 1
Author(s):
Xiaonan Zhang
◽
Xiaoliang Bai
Keyword(s):
Low Power
◽
Low Power Design
◽
Process Variability
◽
Nanometer Cmos
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Independent-Double-Gate FINFET SRAM Cell for Drastic Leakage Current Reduction
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_5
◽
2010
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pp. 67-79
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Cited By ~ 1
Author(s):
Kazuhiko Endo
◽
Shin-ichi O’uchi
◽
Yuki Ishikawa
◽
Yongxun Liu
◽
Takashi Matsukawa
◽
...
Keyword(s):
Leakage Current
◽
Double Gate
◽
Sram Cell
◽
Current Reduction
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On-Chip Circuit Technique for Measuring Jitter and Skew with Picosecond Resolution
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_15
◽
2010
◽
pp. 203-217
Author(s):
K. A. Jenkins
◽
Z. Xu
◽
A. P. Jose
◽
K. L. Shepard
Keyword(s):
On Chip
◽
Circuit Technique
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CMOS Logic Gates Leakage Modeling Under Statistical Process Variations
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_14
◽
2010
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pp. 191-202
Author(s):
Carmelo D’Agostino
◽
Philippe Flatresse
◽
Edith Beigne
◽
Marc Belleville
Keyword(s):
Logic Gates
◽
Process Variations
◽
Statistical Process
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Threshold Voltage Shift Instability Induced by Plasma Charging Damage in MOSFETS with High-K Dielectric
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_7
◽
2010
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pp. 97-106
Author(s):
Koji Eriguchi
◽
Masayuki Kamei
◽
Kenji Okada
◽
Hiroaki Ohta
◽
Kouichi Ono
Keyword(s):
Threshold Voltage
◽
Threshold Voltage Shift
◽
Voltage Shift
◽
High K
◽
High K Dielectric
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Metal Gate Effects on a 32 nm Metal Gate Resistor
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_6
◽
2010
◽
pp. 81-93
Author(s):
Thuy Dao
◽
Ik_Sung Lim
◽
Larry Connell
◽
Dina H. Triyoso
◽
Youngbog Park
◽
...
Keyword(s):
Metal Gate
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Synergy Between Design and Technology: A Key Factor in the Evolving Microelectronic Landscape
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_1
◽
2010
◽
pp. 3-13
Author(s):
Michel Brillouët
Keyword(s):
Design And Technology
◽
Key Factor
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CMOS SOI Technology for WPAN: Application to 60 GHZ LNA
Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits
◽
10.1007/978-90-481-9379-0_9
◽
2010
◽
pp. 123-130
◽
Cited By ~ 3
Author(s):
A. Siligaris
◽
C. Mounet
◽
B. Reig
◽
P. Vincent
◽
A. Michel
Keyword(s):
60 Ghz
◽
Soi Technology
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