FPGA Implementation of the Selected Parts of the Fast Image Segmentation

2012 ◽  
pp. 203-216
Author(s):  
Maciej Wielgosz ◽  
Ernest Jamro ◽  
Dominik Żurek ◽  
Kazimierz Wiatr
Keyword(s):  
Image Segmentation ◽  
Fpga Implementation

Comparison of GPU and FPGA Implementation of SVM Algorithm for Fast Image Segmentation

2013 ◽  
pp. 292-302 ◽  
Author(s):  
Marcin Pietron ◽  
Maciej Wielgosz ◽  
Dominik Zurek ◽  
Ernest Jamro ◽  
Kazimierz Wiatr
Keyword(s):  
Image Segmentation ◽  
Fpga Implementation ◽  
Svm Algorithm

FPGA IMPLEMENTATION OF HIGH SPEED AND LOW POWER ARCHITECTURES FOR IMAGE SEGMENTATION USING SOBEL OPERATORS

2012 ◽  
Vol 21 (07) ◽  
pp. 1250050 ◽  
Author(s):  
ABDUL RAOUF KHALID ◽  
ROY PAILY
Keyword(s):  
Image Segmentation ◽  
Low Power ◽  
High Speed ◽  
Fpga Implementation ◽  
Memory Access ◽  
Clock Frequency ◽  
Dynamic Power ◽  
Optimum Speed ◽  
Low Power Architectures ◽  
Sobel Operators

In this paper we present two architectures for image segmentation using Sobel Operators. The first architecture is designed for optimum speed whereas the second one is designed for low power. To improve the speed of operation and to reduce the memory access two identical processing units operate parallelly. The first architecture is able to segment up to 800 images each of 640 × 480 pixels in one second at 500 MHz clock frequency consuming 27.31 mW dynamic power. The second architecture is able to segment up to 488 images each of 640 × 480 pixels in one second at 300 MHz clock frequency consuming 13.6 mW dynamic power.

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