Low Power Checks in Multi Voltage Designs

Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

Power Minimization Architecture for Multimodal Biometric System using Cadence

Physiological or behavioral characteristics of a person being identified or verified using biometric systems. The preprocessing block has the fir filter in which enhanced energy-efficiency has been obtained by introducing the low power architectures within it. The implementation of low power architectures in the fir filter part will further provide the optimization in the various parameters such as power, area and timing. Therefore, this will help us to do the biometrics process faster and efficient.