SRAM Memory Cell Leakage Reduction Design Techniques in 65 nm Low Power PD-SOI CMOS

Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits ◽

10.1007/978-90-481-9379-0_10 ◽

2010 ◽

pp. 131-139

Author(s):

Olivier Thomas ◽

Marc Belleville ◽

Richard Ferrant

Keyword(s):

Low Power ◽

Memory Cell ◽

Leakage Reduction ◽

Sram Memory ◽

Cell Leakage ◽

Soi Cmos ◽

Design Techniques

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SRAM memory cell leakage reduction design techniques in 65nm low power PD-SOI CMOS

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567244 ◽

2008 ◽

Author(s):

Olivier Thomas ◽

Marc Belleville ◽

Richard Ferrant

Keyword(s):

Low Power ◽

Memory Cell ◽

Leakage Reduction ◽

Sram Memory ◽

Cell Leakage ◽

Soi Cmos ◽

Design Techniques

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High-speed reduced-leakage SRAM memory cell design techniques for low-power 65nm FD-SOI/SON CMOS technology

Microelectronics Journal ◽

10.1016/j.mejo.2014.04.032 ◽

2014 ◽

Vol 45 (7) ◽

pp. 848-856 ◽

Author(s):

Deepon Saha ◽

Subir Kumar Sarkar

Keyword(s):

Low Power ◽

Memory Cell ◽

Cmos Technology ◽

Cell Design ◽

Sram Memory ◽

Design Techniques

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An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications

Asian Journal of Research in Social Sciences and Humanities ◽

10.5958/2249-7315.2017.00035.1 ◽

2017 ◽

Vol 7 (1) ◽

pp. 962 ◽

Author(s):

K. Gavaskar ◽

U. S. Ragupathy

Keyword(s):

Low Power ◽

Memory Cell ◽

Efficient Design ◽

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Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2006.891494 ◽

2007 ◽

Vol 42 (3) ◽

pp. 689-702 ◽

Author(s):

David Levacq ◽

Vincent Dessard ◽

Denis Flandre

Keyword(s):

Low Power ◽

Memory Cell ◽

Ultra Low Power ◽

Low Leakage ◽

Power Diode ◽

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A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) ◽

10.1109/soi.1999.819860 ◽

2003 ◽

Author(s):

S.C. Liu ◽

J.B. Kuo

Keyword(s):

Cell Structure ◽

Memory Cell ◽

Dynamic Threshold ◽

Sram Memory ◽

Threshold Technique ◽

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Low Power and Reliable SRAM Memory Cell and Array Design

10.1007/978-3-642-19568-6 ◽

2011 ◽

Keyword(s):

Low Power ◽

Memory Cell ◽

Array Design ◽

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Hardening a memory cell for low power operation by gate leakage reduction

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2012.6378203 ◽

2012 ◽

Author(s):

Jianping Gong ◽

Yong-Bin Kim ◽

Fabrizio Lombardi ◽

Jie Han

Keyword(s):

Low Power ◽

Memory Cell ◽

Gate Leakage ◽

Leakage Reduction ◽

Power Operation

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Simulation-Based Power Estimation of Low Power MD5 Design Techniques

Modern Environmental Science and Engineering ◽

10.15341/mese(2333-2581)/09.02.2016/007 ◽

2016 ◽

Vol 2 (09) ◽

pp. 625-630

Author(s):

Shamsiah Binti Suhaili ◽

Takahiro Watanabe

Keyword(s):

Low Power ◽

Power Estimation ◽

Simulation Based ◽

Design Techniques

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MODELLING OF NEXT ZEN MEMORY CELL USING LOW POWER CONSUMING HIGH SPEED NANO DEVICES

International Journal of Research in Engineering and Technology ◽

10.15623/ijret.2015.0404115 ◽

2015 ◽

Vol 04 (04) ◽

pp. 670-675

Author(s):

Jayanta Gope .

Keyword(s):

Low Power ◽

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Subthreshold Leakage reduction Strategies for the Design of Low Power Sram

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.1.4.2590 ◽

2013 ◽

Vol 1 (4) ◽

pp. 6-13

Author(s):

Vanitha . ◽

◽

M. Parimaladevi ◽

D. Sharmila ◽

◽

...

Keyword(s):

Low Power ◽

Leakage Reduction ◽

Reduction Strategies ◽

Subthreshold Leakage

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