Design and Characterization of an ASIC Standard Cell Library Industry–Academia Chip Collaborative Project

Author(s):  
M. Naga Lavanya ◽  
M. Pradeep
Author(s):  
Kenza Charafeddine ◽  
Faissal Ouardi

<p>The following work shows an innovative approach to model the timing of<br />standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work,<br />characterization of cells of a standard cell library is done in an hour whereas<br />it is done in 650 hours with the classical method. Also, a method for<br />validating and verification of the precision of the modelled data is presented<br />by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.</p>


Author(s):  
Sukanya Sagarika Meher ◽  
Jushya Ravi ◽  
Mustafa Eren Celik ◽  
Stephen Miller ◽  
Anubhav Sahu ◽  
...  

Author(s):  
Laysson Oliveira Luz ◽  
Jose Augusto M. Nacif ◽  
Ricardo S. Ferreira ◽  
Omar P. Vilela Neto

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