New voltage and temperature scalable gate delay model applied to a 14nm technology

The following work shows an innovative approach to model the timing of standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work, characterization of cells of a standard cell library is done in an hour whereas it is done in 650 hours with the classical method. Also, a method for validating and verification of the precision of the modelled data is presented by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.

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Standard Cell Library Characterization of 28nm Process Based on Machine Learning

DEStech Transactions on Computer Science and Engineering ◽

10.12783/dtcse/cst2017/12552 ◽

2017 ◽

Author(s):

Yi-qi SHE ◽

Li-jun ZHANG ◽

Jian-bin ZHENG ◽

Ai-lin ZHANG ◽

Yue-ping ZHU ◽

...

Keyword(s):

Machine Learning ◽

Standard Cell ◽

Standard Cell Library ◽

Cell Library ◽

Library Characterization

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A Novel Approach to Unsupervised Automated Extraction of Standard Cell Library for Reverse Engineering and Hardware Assurance

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0249 ◽

2019 ◽

Author(s):

Ronald Wilson ◽

Rabin Y. Acharya ◽

Domenic Forte ◽

Navid Asadizanjani ◽

Damon Woodard

Keyword(s):

Reverse Engineering ◽

Integrated Circuit ◽

Contact Layer ◽

Layer By Layer ◽

Standard Cell ◽

High Definition ◽

Standard Cell Library ◽

Cell Library ◽

Standard Cells ◽

Novel Approach

Abstract Reverse engineering today is supported by several tools, such as ICWorks, that assist in the processing and extraction of logic elements from high definition layer by layer images of integrated circuits. To the best of our knowledge, they all work under the assumption that the standard cell library used in the design process of the integrated circuit is available. However, in situations where reverse engineering is done on commercial off-the-shelf components, this information is not available thereby, rendering the assumption invalid. Until now, this problem has not been addressed. In this paper, we introduce a novel approach for the extraction of standard cell library using the contact layer from these images. The approach is completely automated and does not require any prior knowledge on the construction or layout of the target semiconductor integrated circuit. The performance of the approach is evaluated on two AES designs with 10,000 cells compiled from standard libraries with 32nm and 90nm node technologies having 350 and 340 standard cells respectively. We were able to successfully extract 94% and 60% of the standard cells from the 32nm and 90nm AES designs using the proposed approach. We also perform a case study using a realworld sample extracted from a smartcard. Finally, we also investigate the various challenges involved in the extraction of standard cells from images and the steps involved in resolving them.

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