An Augmented Line Segment-Based Algorithm with Delayed Overlap Consideration and Reconfigurable Logic for RSMT Problem

2018 ◽  
pp. 565-574
Author(s):  
V. Vani ◽  
G. R. Prasad
Keyword(s):  
Line Segment ◽  
Reconfigurable Logic

Less is more: Simple stimuli provoke more variable search strategies.

2020 ◽  
Author(s):  
Anna Nowakowska ◽  
Alasdair D F Clarke ◽  
Jessica Christie ◽  
Josephine Reuther ◽  
Amelia R. Hunt
Keyword(s):  
Line Segment ◽  
Search Strategies ◽  
Complex Objects ◽  
Search Behaviour ◽  
Line Segments ◽  
Surface Level ◽  
Efficient Search ◽  
Less Is More ◽  
Dramatic Shift

We measured the efficiency of 30 participants as they searched through simple line segment stimuli and through a set of complex icons. We observed a dramatic shift from highly variable, and mostly inefficient, strategies with the line segments, to uniformly efficient search behaviour with the icons. These results demonstrate that changing what may initially appear to be irrelevant, surface-level details of the task can lead to large changes in measured behaviour, and that visual primitives are not always representative of more complex objects.

AG3line: Active grouping and geometry-gradient combined validation for fast line segment extraction

2021 ◽  
Vol 113 ◽  
pp. 107834
Author(s):  
Yongjun Zhang ◽  
Dong Wei ◽  
Yansheng Li
Keyword(s):  
Line Segment

Real-time, High-resolution Depth Upsampling on Embedded Accelerators

2021 ◽  
Vol 20 (3) ◽  
pp. 1-22
Author(s):  
David Langerman ◽  
Alan George
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Real Time ◽  
Mixed Reality ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Reconfigurable Logic ◽  
Depth Sensors ◽  
Time Requirements ◽  
Graphics Processing

High-resolution, low-latency apps in computer vision are ubiquitous in today’s world of mixed-reality devices. These innovations provide a platform that can leverage the improving technology of depth sensors and embedded accelerators to enable higher-resolution, lower-latency processing for 3D scenes using depth-upsampling algorithms. This research demonstrates that filter-based upsampling algorithms are feasible for mixed-reality apps using low-power hardware accelerators. The authors parallelized and evaluated a depth-upsampling algorithm on two different devices: a reconfigurable-logic FPGA embedded within a low-power SoC; and a fixed-logic embedded graphics processing unit. We demonstrate that both accelerators can meet the real-time requirements of 11 ms latency for mixed-reality apps. 1

Reconfigurable logic-memory hybrid device based on ferroelectric Hf0.5Zr0.5O2

2021 ◽  
pp. 1-1
Author(s):  
Ruiting Zhao ◽  
Xiaoyue Zhao ◽  
Houfang Liu ◽  
Minghao Shao ◽  
Qixin Feng ◽  
...  
Keyword(s):  
Reconfigurable Logic ◽  
Hybrid Device

An Efficient Improved Algorithm of Convex Hull

2014 ◽  
Vol 602-605 ◽  
pp. 3104-3106
Author(s):  
Shao Hua Liu ◽  
Jia Hua Zhang
Keyword(s):  
Convex Hull ◽  
Line Segment ◽  
Main Idea ◽  
Discrete Point ◽  
Directed Line ◽  
Generation Algorithm ◽  
Simple Program ◽  
Point Set ◽  
High Computational Efficiency ◽  
Improved Algorithm

This paper introduced points and directed line segment relation judgment method, the characteristics of generation and Graham method using the original convex hull generation algorithm of convex hull discrete points of the convex hull, an improved algorithm for planar discrete point set is proposed. The main idea is to use quadrilateral to divide planar discrete point set into five blocks, and then by judgment in addition to the four district quadrilateral internally within the point is in a convex edge. The result shows that the method is relatively simple program, high computational efficiency.

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