An Efficient Nearest Neighbor Design for 2D Quantum Circuits

2019 ◽  
pp. 215-231 ◽  
Author(s):  
A. Bhattacharjee ◽  
C. Bandyopadhyay ◽  
B. Mondal ◽  
Robert Wille ◽  
Rolf Drechsler ◽  
...  
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuits

Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture

2017 ◽  
pp. 248-253 ◽  
Author(s):  
Leniency Marbaniang ◽  
Abhoy Kole ◽  
Kamalika Datta ◽  
Indranil Sengupta
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuits

scholarly journals Nearest Neighbor Transformation of Quantum Circuits in 2D Architecture

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 222466-222475
Author(s):  
Xueyun Cheng ◽  
Zhijin Guan ◽  
Pengcheng Zhu
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuits

scholarly journals An Innovative Genetic Algorithm for the Quantum Circuit Compilation Problem

2019 ◽  
Vol 33 ◽  
pp. 7707-7714
Author(s):  
Riccardo Rasconi ◽  
Angelo Oddi
Keyword(s):  
Genetic Algorithm ◽  
Nearest Neighbor ◽  
Quantum Algorithms ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Heuristic Function ◽  
Circuit Realization ◽  
Benchmark Instances ◽  
Technological Limitations ◽  
Selection Of

Quantum Computing represents the next big step towards speed boost in computation, which promises major breakthroughs in several disciplines including Artificial Intelligence. This paper investigates the performance of a genetic algorithm to optimize the realization (compilation) of nearest-neighbor compliant quantum circuits. Currrent technological limitations (e.g., decoherence effect) impose that the overall duration (makespan) of the quantum circuit realization be minimized, and therefore the makespanminimization problem of compiling quantum algorithms on present or future quantum machines is dragging increasing attention in the AI community. In our genetic algorithm, a solution is built utilizing a novel chromosome encoding where each gene controls the iterative selection of a quantum gate to be inserted in the solution, over a lexicographic double-key ranking returned by a heuristic function recently published in the literature.Our algorithm has been tested on a set of quantum circuit benchmark instances of increasing sizes available from the recent literature. We demonstrate that our genetic approach obtains very encouraging results that outperform the solutions obtained in previous research against the same benchmark, succeeding in significantly improving the makespan values for a great number of instances.

Considering nearest neighbor constraints of quantum circuits at the reversible circuit level

2013 ◽  
Vol 13 (2) ◽  
pp. 185-199 ◽  
Author(s):  
Robert Wille ◽  
Aaron Lye ◽  
Rolf Drechsler
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuits ◽  
Reversible Circuit

scholarly journals Synthesis of quantum circuits in Linear Nearest neighbor Model using Positive Davio Lattices

2011 ◽  
Vol 24 (1) ◽  
pp. 71-87 ◽  
Author(s):  
Marek Perkowski ◽  
Martin Lukac ◽  
Dipal Shah ◽  
Michitaka Kameyama
Keyword(s):  
Nearest Neighbor ◽  
Dimensional Space ◽  
Synthesis Method ◽  
Logic Synthesis ◽  
Quantum Circuits ◽  
Quantum Gates ◽  
Synthesis Methods ◽  
Cost Models ◽  
Quantum Cost ◽  
One Dimensional

We present a logic synthesis method based on lattices that realize quantum arrays in One-Dimensional Ion Trap technology. This means that all gates are built from 2x2 quantum primitives that are located only on neighbor qubits in a one-dimensional space (called also vector of qubits or Linear Nearest Neighbor (LNN) architecture). The Logic circuits designed by the proposed method are realized only with 3*3 Toffoli, Feynman and NOT quantum gates and the usage of the commonly used multi-input Toffoli gates is avoided. This realization method of quantum circuits is different from most of reversible circuits synthesis methods from the literature that use only high level quantum cost based on the number of quantum gates. Our synthesis approach applies to both standard and LNN quantum cost models. It leads to entirely new CAD algorithms for circuit synthesis and substantially decreases the quantum cost for LNN quantum circuits. The drawback of synthesizing circuits in the presented LNN architecture is the addition of ancilla qubits.

Analyzing Heuristic-based Randomized Search Strategies for the Quantum Circuit Compilation Problem

2020 ◽  
Vol 174 (3-4) ◽  
pp. 259-281
Author(s):  
Angelo Oddi ◽  
Riccardo Rasconi
Keyword(s):  
Quantum Computing ◽  
Nearest Neighbor ◽  
Quantum Algorithm ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Quantum Gates ◽  
Ranking Functions ◽  
Solution Quality ◽  
Circuit Realization ◽  
Definition Of

In this work we investigate the performance of greedy randomised search (GRS) techniques to the problem of compiling quantum circuits to emerging quantum hardware. Quantum computing (QC) represents the next big step towards power consumption minimisation and CPU speed boost in the future of computing machines. Quantum computing uses quantum gates that manipulate multi-valued bits (qubits). A quantum circuit is composed of a number of qubits and a series of quantum gates that operate on those qubits, and whose execution realises a specific quantum algorithm. Current quantum computing technologies limit the qubit interaction distance allowing the execution of gates between adjacent qubits only. This has opened the way to the exploration of possible techniques aimed at guaranteeing nearest-neighbor (NN) compliance in any quantum circuit through the addition of a number of so-called swap gates between adjacent qubits. In addition, technological limitations (decoherence effect) impose that the overall duration (makespan) of the quantum circuit realization be minimized. One core contribution of the paper is the definition of two lexicographic ranking functions for quantum gate selection, using two keys: one key acts as a global closure metric to minimise the solution makespan; the second one is a local metric, which favours the mutual approach of the closest qstates pairs. We present a GRS procedure that synthesises NN-compliant quantum circuits realizations, starting from a set of benchmark instances of different size belonging to the Quantum Approximate Optimization Algorithm (QAOA) class tailored for the MaxCut problem. We propose a comparison between the presented meta-heuristics and the approaches used in the recent literature against the same benchmarks, both from the CPU efficiency and from the solution quality standpoint. In particular, we compare our approach against a reference benchmark initially proposed and subsequently expanded in [1] by considering: (i) variable qubit state initialisation and (ii) crosstalk constraints that further restrict parallel gate execution.

Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy

2020 ◽  
Vol 29 (16) ◽  
pp. 2050263
Author(s):  
Anirban Bhattacharjee ◽  
Chandan Bandyopadhyay ◽  
Bappaditya Mondal ◽  
Hafizur Rahaman
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Physical Realization ◽  
Emerging Trends ◽  
Look Ahead ◽  
Wide Range ◽  
Clustering Approach ◽  
On Chip ◽  
The Impact

In the last couple of years, quantum computing has come out as emerging trends of computation not only due to its immense popularity but also for its commitment towards physical realization of quantum circuit in on-chip units. At the same time, the process of physical realization has faced several design constraints and one such problem is nearest neighbor (NN) enforcement which demands all the operating qubits to be placed adjacent in the implementable circuit. Though SWAP gate embedment can transform a design into NN architecture, it still creates overhead in the design. So, designing algorithms to restrict the use of SWAPs bears high importance. Considering this fact, in this work, we are proposing a heuristic-based improved qubit placement strategy for efficient implementation of NN circuit. Two different design policies are being developed here. In the first scheme, a global reordering technique based on clustering approach is shown. In the second scheme, a local reordering technique based on look-ahead policy is developed. This look-ahead strategy considers the impact over the gates in the circuit and thereby estimates the effect using a cost metric to decide the suitable option for SWAP implementation. Furthermore, the joint use of both the ordering schemes also has been explored here. To ascertain the correctness of our design algorithms, we have tested them over a wide range of benchmarks and the obtained results are compared with some state-of-the-art design approaches. From this comparison, we have witnessed a considerable reduction on SWAP cost in our design scheme against the reported works’ results.

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