Universal Shift Register Designed at Low Supply Voltages in 20 nm FinFET Using Multiplexer

2021 ◽  
pp. 203-212
Author(s):  
Rajeev Ratna Vallabhuni ◽  
Jujavarapu Sravana ◽  
Chandra Shaker Pittala ◽  
Mikkili Divya ◽  
B. M. S. Rani ◽  
...  
Keyword(s):  
Shift Register ◽  
Universal Shift Register ◽  
Supply Voltages ◽  
20 Nm

Universal Shift Register Designed at Low Supply Voltages in 15 nm CNTFET Using Multiplexer

2021 ◽  
pp. 597-605
Author(s):  
Rajeev Ratna Vallabhuni ◽  
M. Saritha ◽  
Sruthi Chikkapally ◽  
Vallabhuni Vijay ◽  
Chandra Shaker Pittala ◽  
...  
Keyword(s):  
Shift Register ◽  
Universal Shift Register ◽  
Supply Voltages

A novel QCA implementation of MUX-based universal shift register

2013 ◽  
Vol 13 (1) ◽  
pp. 198-210 ◽  
Author(s):  
Reza Sabbaghi-Nadooshan ◽  
Moein Kianpour
Keyword(s):  
Shift Register ◽  
Universal Shift Register

scholarly journals Analysis and Design of Universal Shift Register Using Pulsed Latches

2019 ◽  
Vol 8 (03) ◽  
pp. 10-16
Author(s):  
Mr. Dharmesh Dhabliya, Dr.S.A.Sivakumar
Keyword(s):  
Normal Force ◽  
Shift Register ◽  
Clock Rate ◽  
Analysis And Design ◽  
Low Level ◽  
Universal Shift Register

Power utilization and die region space are the significant boundaries which are considered for structuring low level power outcomes. This paper put forward the structure of low force general move register and 4-piece counter utilizing pipe rationale. Since flip failures are an innate structure hinder in a few applications, different flip lemon are over viewed and executed in widespread move register and 4-piece counter. Flip lemon utilizing pipe rationale is viewed as dependent on the correlation of intensity and region. At last, a low force all inclusive move register and 4-piece counter is planned utilizing pipe rationale. The proposed USR and 4-piece counters are mimicked with various clock rate going from 100 KHz to 500MHz. Re-enactment of these flip flounders, the widespread move register and the 4-piece counters are finished utilizing Tanner device at 180nm innovation. The normal force and the PDP of USR are improved by 33% and 27% and further the normal force and the PDP of 4-piece counter are improved by 36.9% and 30.2% when contrasted and existing plan separately. So the put forward plan is reasonable for low level power and elite applications.

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

2018 ◽  
Vol 16 (02) ◽  
pp. 1850016 ◽  
Author(s):  
H. Maity ◽  
A. Biswas ◽  
A. K. Bhattacharjee ◽  
A. Pal
Keyword(s):  
Quantum Computing ◽  
Logic Gate ◽  
Logic Gates ◽  
Reversible Logic ◽  
Shift Register ◽  
Optimized Design ◽  
Quantum Cost ◽  
Universal Shift Register ◽  
Reversible Logic Gates

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

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