A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata

2019 ◽  
pp. 455-467 ◽  
Author(s):  
Mrinal Goswami ◽  
Mayukh Roy Choudhury ◽  
Bibhash Sen
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Memory Designing Using Quantum-Dot Cellular Automata: Systematic Literature Review, Classification and Current Trends

2017 ◽  
Vol 26 (12) ◽  
pp. 1730004 ◽  
Author(s):  
Sonia Afrooz ◽  
Nima Jafari Navimipour
Keyword(s):  
Cellular Automata ◽  
Literature Review ◽  
Quantum Dot ◽  
Systematic Literature Review ◽  
Random Access ◽  
Memory Cell ◽  
Memory State ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Advantages And Disadvantages

Quantum-dot cellular automata (QCA) has come out as one of the potential computational structures for the emerging nanocomputing systems. It has a large capacity in the development of circuits with high space density and dissipation of low heat and allows faster computers to develop with lower power consumption. The QCA is a new appliance to realize nanolevel digital devices and study and analyze their various parameters. It is also a potential technology for low force and high-density memory plans. Large memory designs in QCA show unique features because of their architectural structure. In QCA-based architectures, memory must be maintained in motion, i.e., the memory state has to be continuously moved through a set of QCA cells. These architectures have different features, such as the number of bits stored in a loop, access type (serial or parallel) and cell arrangement for the memory bank. However, the decisive features of the QCA memory cell design are the number of cells, to put off the use of energy. Although the review and study of the QCA-based memories are very important, there is no complete and systematic literature review about the systematical analyses of the state of the mechanisms in this field. Therefore, there are five main types to provide systematic reviews about the QCA-based memories; including read only memory (ROM), register, flip-flop, content addressable memory (CAM) and random access memory (RAM). Also, it has provided the advantages and disadvantages of the reviewed mechanisms and their important challenges so that some interesting lines for any coming research are provided.

Fredkin gate based energy efficient reversible D flip flop design in quantum dot cellular automata

2020 ◽  
Author(s):  
Syed Farah Naz ◽  
Suhaib Ahmed ◽  
Sparsh Sharma ◽  
Firdous Ahmad ◽  
D. Ajitha
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Energy Efficient ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Fredkin Gate

scholarly journals Design of efficient N‐bit shift register using optimized D flip flop in quantum dot cellular automata technology

2021 ◽  
Author(s):  
Salma Yaqoob ◽  
Suhaib Ahmed ◽  
Syed Farah Naz ◽  
Sadaf Bashir ◽  
Sparsh Sharma
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Shift Register ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata

Energy Efficient Configurable Layout of Logic Block in QCA frame work for an FPGA

2020 ◽  
Vol 12 ◽  
Author(s):  
Arindam Sadhu ◽  
Rimpa Dey Sarkar ◽  
Kunal Das ◽  
Debashis De ◽  
Maitreyi Ray Kanjilal
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Embedded System ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Average Energy ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Logic Block

Aims: Embedded system plays a vital role in today’s life. Hence our motivation is concentrated on area-delay-energy efficient embedded system design in post-CMOS technology i.e. QCA. Objectives: The research is focused on area-delay-energy efficient configurable logic block (CLB) design for field programmable gate array architecture (FPGA) with successful simulation based on a next generation technology, Quantum-dot cellular automata. Methodology: Each proposed circuits are designed in post CMOS 4 dot 2 electron technology i.e. QCA(Quantum Dot Cellular Automata) which has been adopted in circuit implementation due to Low power dissipation, high clock frequency and high package density. Functionality of every circuit is verified by QCADesigner. QCAPro tool is used for power dissipation measurement. Results: In contrast a new approach of using de-multiplexer replacing the decoder has been introduced which results in reduction of the average energy dissipation almost 57%. A NOR based D flip-flop memory architecture and multiplexer is also used in the look up table for the configurable logic block. The proposed architecture thus reduces the overall latency. Proposed CLB is consists of 6356 number of QCA cell with covering 7.44 um2 area. Write and read latency of proposed CLB is 12 and 7.25 QCA clock respectively. Conclusion: The presented paper concludes those read and write latency reduction occurs; average energy dissipation, leakage and switching energy dissipation has been reduced massively and ensues an advantage of overall reduction of the latency for the proposed CLB in the process.

Sign in / Sign up

Export Citation Format

Share Document