Combining static worst-case timing analysis and program proof

1996 ◽  
Vol 11 (2) ◽  
pp. 145-171 ◽  
Author(s):  
Roderick Chapman ◽  
Alan Burns ◽  
Andy Wellings
Keyword(s):  
Timing Analysis ◽  
Worst Case ◽  
Program Proof

Timing analysis of worst case with direct NM of OSEK NM

2008 ◽  
Author(s):  
Chang-Wan Son ◽  
Jin-Ho Kim ◽  
Tae-Yoon Moon ◽  
Key-Ho Kwon ◽  
Sung-Ho Hwang ◽  
...  
Keyword(s):  
Timing Analysis ◽  
Worst Case

Static worst-case timing analysis of Ada

1994 ◽  
Vol XIV (5) ◽  
pp. 88-91 ◽  
Author(s):  
Roderick Chapman ◽  
Alan Burns ◽  
Andy Wellings
Keyword(s):  
Timing Analysis ◽  
Worst Case

Worst case timing analysis of RISC processors: R3000/R3010 case study

2002 ◽  
Author(s):  
Yerang Hur ◽  
Young Hyun Bae ◽  
Sung-Soo Lim ◽  
Sung-Kwan Kim ◽  
Byung-Do Rhee ◽  
...  
Keyword(s):  
Timing Analysis ◽  
Worst Case

A worst case timing analysis technique for instruction prefetch buffers

1994 ◽  
Vol 40 (10-12) ◽  
pp. 681-684 ◽  
Author(s):  
Minsuk Lee ◽  
Sang Lyul Min ◽  
Chong Sang Kim
Keyword(s):  
Timing Analysis ◽  
Worst Case ◽  
Analysis Technique

scholarly journals Efficient worst case timing analysis of data caching

2002 ◽  
Author(s):  
Sung-Kwan Kim ◽  
Sang Lyul Min ◽  
Rhan Ha
Keyword(s):  
Timing Analysis ◽  
Worst Case ◽  
Data Caching

scholarly journals Accurate Estimation of Power Consumption for Binary Comparator System using Back Tracking

2021 ◽  
Vol 19 (2) ◽  
Author(s):  
Mangal Deep Gupta ◽  
‪Rajeev Kumar Chauhan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Timing Analysis ◽  
Logic Gates ◽  
Power Estimation ◽  
Accurate Estimation ◽  
Worst Case ◽  
Simulation Based ◽  
Tracking Model ◽  
Power Delay Product

This paper presents a design of a binary comparator circuit using minimum fan-in logic gates (NAND-NOR) for achieving low power-delay-product (PDP). A 2-bit binary comparator circuit is re-designed to minimize fan-in of logic gates. Utilizing the concept of 2–bit comparator, a general gate-level architecture of a comparator system is proposed for higher input operands. A back-tracking model has been proposed in this work to estimate the worst-case performance in terms of delay and power or PDP for binary comparator circuits. It combines the advantages of the simulation-based method for power estimation and dynamic timing analysis (DTA) techniques for timing analysis. This work has also been extended for 20, 16, 14, 10, and 7-nm FINFET technology. The comparator circuits are simulated on Pyxis schematic tool by Mentor Graphics.

scholarly journals Improving Analytical Delay Modelingfor CMOS Inverters

2015 ◽  
Vol 10 (2) ◽  
pp. 123-134
Author(s):  
Felipe S. Marranghello ◽  
André I. Reis ◽  
Renato P. Ribas
Keyword(s):  
Integrated Circuits ◽  
Timing Analysis ◽  
Channel Length ◽  
Delay Model ◽  
Digital Integrated Circuits ◽  
Cmos Inverter ◽  
Worst Case ◽  
Average Value ◽  
Coupling Capacitance ◽  
Novel Approach

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

scholarly journals A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1976
Author(s):  
Aiguo Bu ◽  
Jie Li
Keyword(s):  
Timing Analysis ◽  
Operating Conditions ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Learning Framework ◽  
Bias Temperature Instability ◽  
Minimal Loss ◽  
Complex Dependence ◽  
Speed Up ◽  
Tremendous Challenge

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

Sign in / Sign up

Export Citation Format

Share Document