scholarly journals A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1976
Author(s):  
Aiguo Bu ◽  
Jie Li
Keyword(s):  
Timing Analysis ◽  
Operating Conditions ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Learning Framework ◽  
Bias Temperature Instability ◽  
Minimal Loss ◽  
Complex Dependence ◽  
Speed Up ◽  
Tremendous Challenge

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

2012 ◽  
pp. 201-230
Author(s):  
Zhenyu Qi ◽  
Yan Zhang ◽  
Mircea Stan
Keyword(s):  
Design Parameters ◽  
Worst Case Analysis ◽  
Transimpedance Amplifier ◽  
Large Area ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Adaptive Computation ◽  
Bias Temperature Instability ◽  
Computation Efficiency ◽  
On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

Investigation of Contribution Ratio Between NBTI and HC Effects in PMOSFETs Under Deep-Submicron Process

2007 ◽  
Author(s):  
Mu-Chun Wang ◽  
Zhen-Ying Hsieh ◽  
Shuang-Yuan Chen ◽  
Heng-Sheng Huang
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Interface State ◽  
Unstable State ◽  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Submicron Process

Quantifying the contribution of the hot carrier effect (HCE) and the negative bias temperature instability (NBTI) effect in PMOSFET device reliability is an urgent target, especially as the dual poly-gate implantation and the novel oxide growth recipe is derived. At this stage, the PMOS gate-oxide thickness is thinner than before, therefore, the implanted boron or BF2 is possible to penetrate from poly gate to surface channel. Furthermore, the implant source contains the plenty ionized hydrogen. This material is easily to be trapped in the gate oxide or bonded with the surface-channel silicon. The amount of interface state concentration, Nit, or oxide trap concentration, Not, is increased. As a result, the threshold voltage of the PMOSFET will be shifted away from the design target. Therefore, the source/drain current will be influenced and this PMOSFET will usually exhibit an unstable state. In the worst case, the IC chip will fail or stop working. This negative bias temperature instability (NBTI) effect has the tremendous impact to the PMOSFET performance.

scholarly journals Impact of negative and positive bias temperature stress on 6T-SRAM cells

2009 ◽  
Vol 7 ◽  
pp. 191-196 ◽  
Author(s):  
S. Drapatz ◽  
G. Georgakos ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Memory Cell ◽  
Oxide Materials ◽  
Positive Bias ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High K ◽  
Bias Temperature Stress ◽  
Degradation Effect

Abstract. With introduction of high-k gate oxide materials, the degradation effect Positive Bias Temperature Instability (PBTI) is starting to play an important role. Together with the still effective Negative Bias Temperature Instability (NBTI) it has significant influence on the 6T SRAM memory cell. We present simulations of both effects, first isolated, then combined in SRAM operation. During long hold of one data, both effects add up to a worst case impact. This leads to an asymmetric cell, which, in a directly following read cycle, combined with the generally unavoidable production variations, maximizes the risk of destructive reading. In future SRAM designs, it will be important to consider this combination of effects to avoid an undesired write event.

Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

2012 ◽  
pp. 284-312
Author(s):  
Zhenyu Qi ◽  
Yan Zhang ◽  
Mircea Stan
Keyword(s):  
Design Parameters ◽  
Worst Case Analysis ◽  
Transimpedance Amplifier ◽  
Large Area ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Adaptive Computation ◽  
Bias Temperature Instability ◽  
Computation Efficiency ◽  
On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

Timing analysis of worst case with direct NM of OSEK NM

2008 ◽  
Author(s):  
Chang-Wan Son ◽  
Jin-Ho Kim ◽  
Tae-Yoon Moon ◽  
Key-Ho Kwon ◽  
Sung-Ho Hwang ◽  
...  
Keyword(s):  
Timing Analysis ◽  
Worst Case

Static worst-case timing analysis of Ada

1994 ◽  
Vol XIV (5) ◽  
pp. 88-91 ◽  
Author(s):  
Roderick Chapman ◽  
Alan Burns ◽  
Andy Wellings
Keyword(s):  
Timing Analysis ◽  
Worst Case

scholarly journals Privacy Preserving Machine Learning with Homomorphic Encryption and Federated Learning

2021 ◽  
Vol 13 (4) ◽  
pp. 94
Author(s):  
Haokun Fang ◽  
Quan Qian
Keyword(s):  
Machine Learning ◽  
Homomorphic Encryption ◽  
Privacy Preserving ◽  
Great Success ◽  
Learning Framework ◽  
Computational Overhead ◽  
Important Concern ◽  
Speed Up ◽  
Key Length ◽  
Core Idea

Privacy protection has been an important concern with the great success of machine learning. In this paper, it proposes a multi-party privacy preserving machine learning framework, named PFMLP, based on partially homomorphic encryption and federated learning. The core idea is all learning parties just transmitting the encrypted gradients by homomorphic encryption. From experiments, the model trained by PFMLP has almost the same accuracy, and the deviation is less than 1%. Considering the computational overhead of homomorphic encryption, we use an improved Paillier algorithm which can speed up the training by 25–28%. Moreover, comparisons on encryption key length, the learning network structure, number of learning clients, etc. are also discussed in detail in the paper.

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