High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond

2009 ◽  
Author(s):  
D.-G. Park ◽  
K. Stein ◽  
K. Schruefer ◽  
Y. Lee ◽  
J.-P. Han ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Low Power ◽  
Critical Path ◽  
Logic Circuits ◽  
Metal Gate ◽  
Bulk Technology

32nm gate-first high-k/metal-gate technology for high performance low power applications

2008 ◽  
Author(s):  
C. H. Diaz ◽  
K. Goto ◽  
H.T. Huang ◽  
Yuri Yasuda ◽  
C.P. Tsao ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Metal Gate ◽  
High K

scholarly journals Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function

2011 ◽  
Vol 2 (1) ◽  
pp. 11-24 ◽  
Author(s):  
Deepesh Ranka ◽  
Ashwani K. Rana ◽  
Rakesh Kumar Yadav ◽  
Kamalesh Yadav ◽  
Devendra Giri
Keyword(s):  
Performance Evaluation ◽  
Work Function ◽  
Metal Gate ◽  
Gate Work Function

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

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