A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

Cascoded GaN half-bridge with 17-MHz wide-band galvanically isolated current sensor

A cascoded GaN half-bridge with wide-band galvanically isolated current sensor is proposed. A 650-V depletion-mode GaN FET is switched by a low-propagation-delay gate driver in active-mode. The standby and active modes are switched by a 25-V N-ch LDMOS. The current sensor uses the LDMOS as a shunt resistor, gm-cell-based sense amplifier and mixer based isolation amplifier for wider bandwidth. PVT variations of on-resistance of the current-detecting MOSFET are compensated using a reference MOSFET. A digital calibration loop across the isolation is formed to keep the current sensor gain constant within ±1.5% across the whole temperature range. The wide-band current sensor can measure power device switching current. In this study, a cascoded GaN half-bridge switching and inductor current sensing using low-side and high-side device current are demonstrated. The proposed techniques show the possibility of implementing a GaN half-bridge module with isolated current sensor in a package.

Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit

High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reduction techniques at the circuit level, such as Power Gating (PG), Drain Gating (DG), LECTOR and GALEOR, and analyzes the effect of PVT variations on the dissipation and delay of leakage power using the ISCAS C17 benchmark circuit.