Design, modelling and system level simulations of DRIE-based MEMS differential capacitive accelerometer

2019 ◽  
Vol 25 (9) ◽  
pp. 3521-3532 ◽  
Author(s):  
R. Mukhiya ◽  
P. Agarwal ◽  
S. Badjatya ◽  
M. Garg ◽  
P. Gaikwad ◽  
...  
Author(s):  
Zakriya Mohammed ◽  
Owais Talaat Waheed ◽  
Ibrahim (Abe) M. Elfadel ◽  
Aveek Chatterjee ◽  
Mahmoud Rasras

The paper demonstrates the design and complete analysis of 1-axis MEMS capacitive accelerometer. The design is optimized for high linearity, high sensitivity, and low cross-axis sensitivity. The noise analysis is done to assure satisfactory performance under operating conditions. This includes the mechanical noise of accelerometer, noise due to interface electronics and noise caused by radiation. The latter noise will arise when such accelerometer is deployed in radioactive (e.g., nuclear power plants) or space environments. The static capacitance is calculated to be 4.58 pF/side. A linear displacement sensitivity of 0.012μm/g (g = 9.8m/s2) is observed in the range of ±15g. The differential capacitive sensitivity of the device is 90fF/g. Furthermore, a low cross-axis sensitivity of 0.024fF/g is computed. The effect of radiation is mathematically modelled and possibility of using these devices in radioactive environment is explored. The simulated noise floor of the device with electronic circuit is 0.165mg/Hz1/2.


Author(s):  
Martin Klaus Muller ◽  
Tomas Dominguez-Bolano ◽  
Jose A. Garcia-Naya ◽  
Luis Castedo ◽  
Markus Rupp

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.


Sign in / Sign up

Export Citation Format

Share Document