Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

2018 ◽  
Vol 57 (7) ◽  
pp. 1948-1960 ◽  
Author(s):  
Moslem Balali ◽  
Abdalhossein Rezai
Keyword(s):  
High Speed ◽  
Low Complexity ◽  
Ripple Carry Adder

Updated Efficient Area -Carry Select Adder for Low Complexity D LATCH Configuration by disease identification in brain tumor hyper spectral image

2019 ◽  
Vol 14 ◽  
Author(s):  
Teresa V.V ◽  
Anand. B
Keyword(s):  
Research Work ◽  
Low Complexity ◽  
Propagation Delay ◽  
Maximum Speed ◽  
Hyper Spectral ◽  
Ripple Carry Adder ◽  
Minimum Power Consumption ◽  
Carry Select Adder ◽  
The Look ◽  
Propagation Result

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

A Low-Complexity Distributed-MIMO Testbed Based on High-Speed Sigma–Delta-Over-Fiber

2019 ◽  
Vol 67 (7) ◽  
pp. 2861-2872 ◽  
Author(s):  
Ibrahim Can Sezgin ◽  
Martin Dahlgren ◽  
Thomas Eriksson ◽  
Mikael Coldrey ◽  
Christina Larsson ◽  
...  
Keyword(s):  
High Speed ◽  
Low Complexity ◽  
Sigma Delta

scholarly journals Layer Morphology and Ink Compatibility of Silver Nanoparticle Inkjet Inks for Near-Infrared Sintering

Nanomaterials ◽  
2020 ◽  
Vol 10 (5) ◽  
pp. 892
Author(s):  
Dieter Reenaers ◽  
Wouter Marchal ◽  
Ianto Biesmans ◽  
Philippe Nivelle ◽  
Jan D’Haen ◽  
...  
Keyword(s):  
Silver Nanoparticle ◽  
High Speed ◽  
Processing Time ◽  
Near Infrared ◽  
Printed Electronics ◽  
Low Cost ◽  
Low Complexity ◽  
Post Processing ◽  
Drop On Demand ◽  
Processing Step

The field of printed electronics is rapidly evolving, producing low cost applications with enhanced performances with transparent, stretchable properties and higher reliability. Due to the versatility of printed electronics, industry can consider the implementation of electronics in a way which was never possible before. However, a post-processing step to achieve conductive structures—known as sintering—limits the production ease and speed of printed electronics. This study addresses the issues related to fast sintering without scarifying important properties such as conductivity and surface roughness. A drop-on-demand inkjet printer is employed to deposit silver nanoparticle-based inks. The post-processing time of these inks is reduced by replacing the conventional oven sintering procedure with the state-of-the-art method, named near-infrared sintering. By doing so, the post-processing time shortens from 30–60 min to 6–8 s. Furthermore, the maximum substrate temperature during sintering is reduced from 200 °C to 120 °C. Based on the results of this study, one can conclude that near-infrared sintering is a ready-to-industrialize post-processing method for the production of printed electronics, capable of sintering inks at high speed, low temperature and with low complexity. Furthermore, it becomes clear that ink optimization plays an important role in processing inkjet printable inks, especially after being near-infrared sintered.

scholarly journals A Fast Hybrid Beamforming Scheme for High-Speed Railway Communications

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 998
Author(s):  
Yu Xiao ◽  
Gang Qiu ◽  
Yafeng Wang
Keyword(s):  
High Speed ◽  
Low Complexity ◽  
Spectrum Efficiency ◽  
System Throughput ◽  
Quality Of Services ◽  
Communication Service ◽  
High Speed Railway ◽  
High Speed Trains ◽  
Hybrid Beamforming

With the increasingly demand for reliable mobile communication service in the high-speed railway (HSR) system, the service stability of HSR communication is of great concern in recent research. Focusing on ensuring the quality of services (QoS) and system throughput, massive multi-input multi-output (massive MIMO) and beamforming technologies have been widely applied. In this paper, aiming to minimize the communication outage probability (OP) and not to decrease spectrum efficiency (SE) too much, we propose a fast HBF (F-HBF) scheme for HSR communications. The proposed scheme uses a low-complexity beam-searching algorithm to trace high-speed trains in real time. The simulation results verify that the proposed scheme can significantly reduce OP without too much SE degradation.

A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection

2019 ◽  
Vol 11 (1) ◽  
pp. 80-87 ◽  
Author(s):  
Jitendra Kumar Saini ◽  
Avireni Srinivasulu ◽  
Renu Kumawat
Keyword(s):  
Mass Production ◽  
High Speed ◽  
Field Effect Transistor ◽  
Full Adder ◽  
Enabling Technology ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Effect Transistor ◽  
Cad Tool ◽  
Power Delay Product

The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.

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