Updated Efficient Area -Carry Select Adder for Low Complexity D LATCH Configuration by disease identification in brain tumor hyper spectral image

2019 ◽  
Vol 14 ◽  
Author(s):  
Teresa V.V ◽  
Anand. B
Keyword(s):  
Research Work ◽  
Low Complexity ◽  
Propagation Delay ◽  
Maximum Speed ◽  
Hyper Spectral ◽  
Ripple Carry Adder ◽  
Minimum Power Consumption ◽  
Carry Select Adder ◽  
The Look ◽  
Propagation Result

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

scholarly journals Modified Low Power Binary to Excess Code Converter

2015 ◽  
Vol 4 (03) ◽  
pp. 06-10
Author(s):  
Ms. Mayuri Ingole
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Major Aspect ◽  
Code Converter ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
The One

Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques. 

scholarly journals Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique

2019 ◽  
Vol 8 (12) ◽  
pp. 2873-2879 ◽  
Keyword(s):  
Optimization Technique ◽  
Vlsi Architecture ◽  
Performance Constraints ◽  
Area Efficiency ◽  
Logic Optimization ◽  
Ripple Carry Adder ◽  
Overall Performance ◽  
Carry Select Adder ◽  
The Cost ◽  
Area Efficient

Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number of full adders when compared to Ripple Carry Adder. Though, the existing adder designing techniques are area efficient, there is still scope to achieve area efficiency as area decides the cost of the VLSI Systems. Not only area-efficient but also power potent architectures are required to accelerate the overall performance of the VLSI systems. To meet these objectives, this paper proposes an efficient VLSI architecture for carry select adder by using logic optimization technique addressing performance constraints. The proposed architecture is designed and implemented using cadence encounter tool for different data widths ranging from 16 bits to 128 bits. The performance of the proposed 128-bit architecture achieves an area improvement of 63.43% and a power improvement of 71.00923% when compared to 128-bit SQRT-CSLA architecture

scholarly journals ОСОБЛИВОСТІ ЗАБЕЗПЕЧЕННЯ АЕРОДИНАМІЧНИХ ХАРАКТЕРИСТИК РЕГІОНАЛЬНОГО ПАСАЖИРСЬКОГО ЛІТАКА

2019 ◽  
pp. 106-133
Author(s):  
Олександр Дмитрович Донець ◽  
Володимир Олександрович Кудрявцев
Keyword(s):  
High Speed ◽  
Research Work ◽  
Flight Dynamics ◽  
Aerodynamic Characteristics ◽  
Static Stability ◽  
Control Mode ◽  
Aviation Industry ◽  
Maximum Speed ◽  
Flight Tests ◽  
Aerodynamic Configuration

Principal results of the computational and research work performed during development of a regional passenger aircraft to ensure its aerodynamic characteristics are given. When creating the An-148-100/An-158 family of aircraft, such level of the aircraft aerodynamic perfection was achieved, which ensured fulfillment of the specified requirements for their flight performance – maximum speed, cruising flight altitude and flight range with different payloads. The developed aerodynamic configuration made it possible to create a family of regional passenger high-wing planes with a flight speed of up to 870 km/h (true speed) (M = 0.8), which have no analogues in the world aviation industry. Developed for the An-148-100 / An- 158 aircraft, supercritical profiles of the new generation with a large maximum relative thickness formed the basis of the aerodynamic configuration of a high-speed  wing with moderate sweep. The aircraft lift-to-drag ratio in cruise flight is Kcruise = 15.8, which corresponds to the worldwide values. Developed aerodynamic configuration of the wing high-lift devices provides high bearing properties of the wing during take-off and landing stages, which allows to fully meet the requirements for the runway required length of the base airfields Lrun = 1485...1950 m. Developed algorithms are implemented in the electric remote control system and provide necessary standard characteristics of stability, controllability and flight dynamics in the main control mode. Selected margins of the aircraft’s own static stability and effectiveness of its controls ensure safe completion of the flight in standby control mode. The certification flight tests of the An-148-100/An-158 airplanes confirmed full compliance of their take-off and landing performance, as well as the stability, controllability and flight dynamics characteristics with the requirements of the Certification basis in both standard and in failure situations tested in flight tests. Necessary and sufficient amount of experimental work was conducted in the lowspeed  and high-speed wind tunnels of the ANTONOV SC and TsAGI to verify the aerodynamic and spin characteristics of the An-148-100/An-158 airplane models, which improved the aerodynamic configuration of the aircraft and its individual units and allowed to apply the work results in calculation of aircraft strength, as well as for development of their systems.

scholarly journals Effective Morphological Transformation and Sub-pixel Classification of Clustered Images

2019 ◽  
Vol 8 (01) ◽  
pp. 08-14
Author(s):  
Mr. B. Naga Rajesh
Keyword(s):  
Time Complexity ◽  
Research Work ◽  
Morphological Operations ◽  
Morphological Transformation ◽  
Structuring Element ◽  
Hyper Spectral ◽  
Hyper Spectral Imaging ◽  
Pixel Scale ◽  
Spatial Regularization

The main aim of this research work is to perform the morphological operations with reduced time complexity and area complexity. Morphological operation is the key element in any image processing. Finding the maximum and minimum using a window of defined size will imply to the morphological dilation and erosion respectively. So the proposed algorithm should be fast in the comparison and sorting, this way the time complexity could be reduced. It’s believed that the anchor concept will fetch this cause. The idea behind this is it fixes a pixel and setting it as the center pixel all the surrounding pixels will be processed. Moreover this is now been implemented for rectangular structuring element. This paper attempts the same for flat and 3D structuring elements. Hyper-spectral Imaging is a developing zone of remote detecting applications. Hyper-spectral pictures incorporate more extravagant and better otherworldly data than the multi-spectral pictures got previously. Hyper-otherworldly pictures are described by an exchange off between the unearthly and spatial resolution. The principle issue of the hyper-ghostly information is the generally low spatial goal. For arrangement, the serious issue brought about by low spatial goal is the blended pixels. Blended pixels alluded to the pixels which are involved by more than one land spread class. In the proposed procedure another strategy is utilized to address the issue of blended pixels and to get a better spatial goal of the land spread characterization maps. The strategy misuses the upsides of both picture bunching methods and phantom dimming calculations, so as to decide the fragmentary plenitudes of the classes at a sub-pixel scale. Spatial regularization by Flank planning method is at last performed to spatially find the got classes at sub-pixel level.

scholarly journals Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and KoggeStone Adder

2019 ◽  
Vol 8 (2) ◽  
pp. 6138-6141
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Propagation Delay ◽  
Fir Filter ◽  
Filter Synthesis ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Effective Performance

32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

2019 ◽  
Vol 8 (10) ◽  
pp. 4288-4296
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Simulation Tools ◽  
Booth Multiplier ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
Reduced Complexity ◽  
Fir Filter Design

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

An efficient architecture for carry select adder

2017 ◽  
Vol 14 (3) ◽  
pp. 249-254 ◽  
Author(s):  
Vaithiyanathan Dhandapani
Keyword(s):  
Power Consumption ◽  
Large Scale ◽  
Vlsi Design ◽  
Vital Role ◽  
Portable Devices ◽  
Switching Activity ◽  
Content Type ◽  
Cell Library ◽  
Ripple Carry Adder ◽  
Carry Select Adder

Purpose Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit. Design/methodology/approach This paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library. Findings Optimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA. Originality/value The efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

Carry-select adder using single ripple-carry adder

1998 ◽  
Vol 34 (22) ◽  
pp. 2101 ◽  
Author(s):  
T.-Y. Chang ◽  
M.-J. Hsiao
Keyword(s):  
Ripple Carry Adder ◽  
Carry Select Adder
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