Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

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A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

Electronics ◽

10.3390/electronics9101733 ◽

2020 ◽

Vol 9 (10) ◽

pp. 1733

Author(s):

Hanbo Jia ◽

Xuan Guo ◽

Xuqiang Zheng ◽

Xiaodi Xu ◽

Danyu Wu ◽

...

Keyword(s):

High Speed ◽

Dynamic Range ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Oxide Semiconductor ◽

Cmos Process ◽

Nyquist Frequency ◽

Least Significant Bit ◽

Analog To Digital ◽

Differential Nonlinearity

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

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A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽

10.3390/electronics8030305 ◽

2019 ◽

Vol 8 (3) ◽

pp. 305 ◽

Cited By ~ 1

Author(s):

Dong Wang ◽

Xiaoge Zhu ◽

Xuan Guo ◽

Jian Luan ◽

Lei Zhou ◽

...

Keyword(s):

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Sar Adc ◽

Oxide Semiconductor ◽

Power Measurement ◽

Cmos Process ◽

Analog To Digital ◽

Full Speed ◽

Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

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A new design for 4-bit RCA using Quantum Cellular Automata Technology

10.21203/rs.3.rs-569937/v1 ◽

2021 ◽

Author(s):

Saeid Seyedi ◽

Behrouz Pourghebleh

Keyword(s):

Cellular Automata ◽

Power Consumption ◽

Cell Count ◽

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Quantum Cellular Automata ◽

Ripple Carry Adder ◽

Efficient Alternative

Abstract Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology due to its excellent potential in developing designs with low-power consumption, high-speed, and high-density has been recognized as a suitable replacement to CMOS technology. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. Adders as the main unit in logic circuits and digital arithmetic play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and due to its remarkable features can be useful to reach circuits with the minimum required area and power consumption. Therefore, in this study, a new design for RCA in QCA technology is recommended to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner version 2.0.3 as a well known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count in comparison to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.

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A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs

Electronics ◽

10.3390/electronics8050589 ◽

2019 ◽

Vol 8 (5) ◽

pp. 589 ◽

Cited By ~ 1

Author(s):

Tianchen Shen ◽

Jiabing Liu ◽

Chunyi Song ◽

Zhiwei Xu

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Critical Path ◽

Complementary Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Cmos Process ◽

Flip Flop ◽

Mode Control ◽

Power Operation

A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation.

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Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

Recent Patents on Engineering ◽

10.2174/1872212112666180810150357 ◽

2019 ◽

Vol 13 (2) ◽

pp. 174-180

Author(s):

Poonam Sharma ◽

Ashwani Kumar Dubey ◽

Ayush Goyal

Keyword(s):

Image Processing ◽

High Speed ◽

Computation Time ◽

Digital Signal ◽

Instruction Set ◽

Computationally Efficient ◽

Specific Instruction ◽

Processor Core ◽

Speed Performance ◽

Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

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Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration

Materials ◽

10.3390/ma14051272 ◽

2021 ◽

Vol 14 (5) ◽

pp. 1272

Author(s):

Zhihua Fan ◽

Qinling Deng ◽

Xiaoyu Ma ◽

Shaolin Zhou

Keyword(s):

Phase Change ◽

Phase Change Materials ◽

Complementary Metal Oxide Semiconductor ◽

Photonic Devices ◽

Oxide Semiconductor ◽

Cmos Process ◽

Nanophotonic Devices ◽

Optoelectronic Integration ◽

Hybrid Devices ◽

Micro Electromechanical System

In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

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CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.7.10915 ◽

2018 ◽

Vol 7 (2.7) ◽

pp. 647

Author(s):

J Lakshmi Prasanna ◽

V Sahiti ◽

E Raghuveera ◽

M Ravi Kumar

Keyword(s):

Complementary Metal Oxide Semiconductor ◽

Logic Gates ◽

Tree Structure ◽

Oxide Semiconductor ◽

Least Significant Bit ◽

Power Efficient ◽

Prefix Tree ◽

Digital Comparator ◽

Parallel Prefix ◽

Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

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Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽

10.3390/s21051683 ◽

2021 ◽

Vol 21 (5) ◽

pp. 1683

Author(s):

Winai Jaikla ◽

Fabian Khateb ◽

Tomasz Kulej ◽

Koson Pitaksuttayaprot

Keyword(s):

Metal Oxide ◽

Dynamic Range ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Experimental Results ◽

Oxide Semiconductor ◽

Cmos Process ◽

Voltage Gain ◽

Universal Filter ◽

Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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Millimeter-wave dual-mode and dual-band switchable Gilbert up-conversion mixer in 65-nm CMOS process

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078721000155 ◽

2021 ◽

pp. 1-5

Author(s):

Fang Zhu ◽

Guo Qing Luo

Keyword(s):

Millimeter Wave ◽

Complementary Metal Oxide Semiconductor ◽

Local Oscillator ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Dual Band ◽

Cmos Process ◽

Pumping Power ◽

Dual Mode ◽

Dc Power

Abstract In this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

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