Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks

2020 ◽  
Vol 36 (3) ◽  
pp. 385-408 ◽  
Author(s):  
Biswajit Bhowmik
Keyword(s):  
Communication Networks ◽  
Open Faults ◽  
On Chip

Performance Analysis of On-Chip Communication Structures under Device Variability

2010 ◽  
Vol 1 (4) ◽  
pp. 40-62
Author(s):  
Faiz-ul Hassan ◽  
Wim Vanderbauwhede ◽  
Fernando Rodríguez-Salazar
Keyword(s):  
Communication Networks ◽  
Data Storage ◽  
Failure Probability ◽  
Analytical Models ◽  
High Yield ◽  
Communication Link ◽  
Link Failure ◽  
Communication Structures ◽  
On Chip ◽  
The Impact

On-chip communication is becoming an important bottleneck in the design and operation of high performance systems where it has to face additional challenges due to device variability. Communication structures such as tapered buffer drivers, interconnects, repeaters, and data storage elements are vulnerable to variability, which can limit the performance of the on-chip communication networks. In this regard, it becomes important to have a complete understanding of the impact that variability will have on the performance of these circuit elements in order to design high yield and reliable systems. In this paper, the authors have characterized the performance of the communication structures under the impact of random dopant fluctuation (RDF) for the future technology generations of 25, 18, and 13 nm. For accurate characterization of their performance, a Monte Carlo simulation method has been used along with predictive device models for the given technologies. Analytical models have been developed for the link failure probability of a repeater inserted interconnect which uses characterization data of all communication structures to give an accurate prediction of the link failure probability. The model has also been extended to calculate the link failure probability of a wider communication link.

scholarly journals Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1196
Author(s):  
Samuel da Silva Oliveira ◽  
Bruno Motta de Carvalho ◽  
Márcio Eduardo Kreutz
Keyword(s):  
Real Time ◽  
Communication Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
Chip Area ◽  
Average Latency ◽  
Real Time Applications ◽  
On Chip

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture

2011 ◽  
pp. 209-234
Author(s):  
Y. Aydi ◽  
M. Baklouti ◽  
Ph. Marquet ◽  
M. Abid ◽  
J.L. Dekeyser
Keyword(s):  
Communication Networks ◽  
Interconnection Networks ◽  
Design Methodology ◽  
Parallel Systems ◽  
Parallel Applications ◽  
Multistage Interconnection Networks ◽  
Networks On Chip ◽  
Data Intensive ◽  
Cost Metrics ◽  
On Chip

Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage networks on chip dedicated to parallel multi-cores architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through data parallel applications with different number of cores. We also show in the proposed framework that multistage interconnection networks are cost-effective high performance networks for parallel SOCs.

scholarly journals Self-Controlling Photonic-on-Chip Networks With Deep Reinforcement Learning

2021 ◽  
Author(s):  
Nguyen Do ◽  
Dung Truong ◽  
Duy Nguyen ◽  
Minh Hoai ◽  
Cuong Pham
Keyword(s):  
Reinforcement Learning ◽  
Power Consumption ◽  
Communication Networks ◽  
Architectural Design ◽  
Transmission Loss ◽  
Linear Chain ◽  
Simulated Data ◽  
Optical Switches ◽  
Photonic Networks ◽  
On Chip

Abstract We present a novel photonic chip design for high bandwidth four-degree optical switches that support high-dimensional switching mechanisms with low insertion loss and low crosstalk in a low power consumption level and a short switching time. Such four-degree photonic chips can be used to build an integrated full-grid Photonic-on-Chip Network (PCN). With four distinct input/output directions, the proposed photonic chips are superior compared to the current bidirectional photonic switches, where a conventionally sizable PCN can only be constructed as a linear chain of bidirectional chips. Our four-directional photonic chips are more flexible and scalable for the design of modern optical switches, enabling the construction of multi-dimensional photonic chip networks that are widely applied for intra-chip communication networks and photonic data centers. More noticeably, our photonic networks can be self-controlling with our proposed Multi-Sample Discovery model, a deep reinforcement learning model based on Proximal Policy Optimization. On a PCN, we can optimize many criteria such as transmission loss, power consumption, and routing time, while preserving performance and scaling up the network with dynamic changes. Experiments on simulated data demonstrate the effectiveness and scalability of the proposed architectural design and optimization algorithm. Perceivable insights make the constructed architecture become the self-controlling photonic-on-chip networks.

Performance Analysis of On-Chip Communication Structures under Device Variability

2012 ◽  
pp. 177-197
Author(s):  
Faiz-ul Hassan ◽  
Wim Vanderbauwhede ◽  
Fernando Rodríguez-Salazar
Keyword(s):  
Communication Networks ◽  
Data Storage ◽  
Failure Probability ◽  
Analytical Models ◽  
High Yield ◽  
Link Failure ◽  
Future Technology ◽  
Communication Structures ◽  
On Chip ◽  
The Impact

On-chip communication is becoming an important bottleneck in the design and operation of high performance systems where it has to face additional challenges due to device variability. Communication structures such as tapered buffer drivers, interconnects, repeaters, and data storage elements are vulnerable to variability, which can limit the performance of the on-chip communication networks. In this regard, it becomes important to have a complete understanding of the impact that variability will have on the performance of these circuit elements in order to design high yield and reliable systems. In this paper, the authors have characterized the performance of the communication structures under the impact of random dopant fluctuation (RDF) for the future technology generations of 25, 18, and 13 nm. For accurate characterization of their performance, a Monte Carlo simulation method has been used along with predictive device models for the given technologies. Analytical models have been developed for the link failure probability of a repeater inserted interconnect which uses characterization data of all communication structures to give an accurate prediction of the link failure probability. The model has also been extended to calculate the link failure probability of a wider communication link.

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