Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

Wireless Personal Communications ◽

10.1007/s11277-017-5028-z ◽

2017 ◽

Vol 98 (4) ◽

pp. 3549-3561 ◽

Author(s):

Geetam Singh Tomar ◽

Marcus Lloyde George

Keyword(s):

Binary Multiplier

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A unified unsigned/signed binary multiplier

Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004. ◽

10.1109/acssc.2004.1399185 ◽

2005 ◽

Author(s):

Guoping Wang

Keyword(s):

Binary Multiplier

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A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106) ◽

10.1109/aspdac.2000.835065 ◽

2002 ◽

Author(s):

H. Sakamoto ◽

H. Ochi ◽

K. Uda ◽

K. Taki ◽

Bu-Yeol Lee ◽

...

Keyword(s):

Low Power ◽

Pass Transistor ◽

Binary Multiplier ◽

Pass Transistor Logic

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Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies ◽

10.1109/icaccct.2014.7019410 ◽

2014 ◽

Author(s):

Abhyarthana Bisoyi ◽

Mitu Baral ◽

Manoja Kumar Senapati

Keyword(s):

Vedic Multiplier ◽

Binary Multiplier

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A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation

Advanced Science Letters ◽

10.1166/asl.2009.1071 ◽

2009 ◽

Vol 2 (3) ◽

pp. 391-397

Author(s):

Ankush Ghosh ◽

Souvik Sarkar ◽

D. Ray Chaudhuri ◽

Subir Kumar Sarkar

Keyword(s):

Circuit Design ◽

Logic Circuit ◽

Power Efficient ◽

Single Spin ◽

Design And Implementation ◽

Binary Multiplier ◽

Multiplier Circuit

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Systolic array for binary multiplier

Proceedings of ICSIPNN '94. International Conference on Speech, Image Processing and Neural Networks ◽

10.1109/sipnn.1994.344804 ◽

2002 ◽

Author(s):

L. Wang ◽

I. Hartimo

Keyword(s):

Systolic Array ◽

Binary Multiplier

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A variable-shift nega-binary multiplier

International Journal of Electronics ◽

10.1080/00207217408900472 ◽

1974 ◽

Vol 36 (6) ◽

pp. 749-751 ◽

Author(s):

GURURAJ S. RAO ◽

M. NAGESH RAO ◽

E. V. KRISHNAMURTHY

Keyword(s):

Binary Multiplier

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VLSI Design and FPGA Implementation of N Binary Multiplier Using N-1 Binary Multipliers

International Journal of Science and Research (IJSR) ◽

10.21275/v5i3.nov161976 ◽

2016 ◽

Vol 5 (3) ◽

pp. 983-987

Keyword(s):

Vlsi Design ◽

Fpga Implementation ◽

Binary Multiplier

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Increasing the Speed of a Multi-bit Binary Multiplier

Problems of advanced micro- and nanoelectronic systems development ◽

10.31114/2078-7707-2018-2-149-155 ◽

2018 ◽

pp. 149-155

Author(s):

A.N. Yakunin ◽

Aung Myo San

Keyword(s):

Binary Multiplier

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Fast and exact multiple‐input unary‐to‐binary multiplier with variable precision for stochastic computing

Electronics Letters ◽

10.1049/el.2020.0206 ◽

2020 ◽

Vol 56 (10) ◽

pp. 482-485

Author(s):

C.F. Chuah ◽

T. Nandha Kumar

Keyword(s):

Stochastic Computing ◽

Variable Precision ◽

Multiple Input ◽

Binary Multiplier

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Modified Partial Product Generator for Redundant Binary Multiplier with High Modularity and Carry-Free Addition

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2017.8026 ◽

2017 ◽

Vol V (VIII) ◽

pp. 182-188

Author(s):

Thoka. Babu Rao

Keyword(s):

Partial Product ◽

Binary Multiplier

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