Background:
For higher order multiplications, a huge number of adders or compressors are used to perform the
addition of the partial products.
Objective:
Hence the area and the propagation delay will increase. Researchers are trying to reduce the numbers of additions
of partial products.
Method:
In this paper, different modified compressor have been proposed and based on that compressors, 16x16-bit binary
multiplier has been discussed.
Results:
The proposed design provide better area, power consumption, critical path delay and less number of transistor
counts when compared to other design using the conventional compressors. Here the proposed method has been used in
Wallace tree multiplier or Dadda tree multiplier. The compressor used here has been implemented using Microwind DSCH
3.8 lite.
Conclusion:
The modified compressor makes the multiplier faster and reduces the number of addition of partial products..
Power Optimization of Binary Multiplier Based on FPGA
