Class-AB Flipped Voltage Follower Cell with High Current Driving Capability and Low Output Resistance for High Frequency Applications

2021 ◽  
Author(s):  
Caffey Jindal ◽  
Rishikesh Pandey
Keyword(s):  
High Frequency ◽  
High Current ◽  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Driving Capability

A class-AB CMOS differential flipped voltage follower with output driving capability up to 100pF

2013 ◽  
Vol 44 (10) ◽  
pp. 930-940 ◽  
Author(s):  
C. Muñiz-Montero ◽  
L.A. Sánchez-Gaspariano ◽  
J.J. Camacho-Escoto ◽  
L.A. Villa-Vargas ◽  
H. Molina-Lozano ◽  
...  
Keyword(s):  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Driving Capability

scholarly journals Class AB flipped voltage follower with very low output resistance and no additional power

2018 ◽  
Vol 15 (4) ◽  
pp. 20171170-20171170 ◽  
Author(s):  
Ivan Padilla-Cantoya ◽  
Jesus E. Molinar-Solis ◽  
Jaime Ramirez-Angulo
Keyword(s):  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower

High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell

2019 ◽  
Vol 28 (08) ◽  
pp. 1950140
Author(s):  
Caffey ◽  
Rishikesh Pandey
Keyword(s):  
Supply Voltage ◽  
Tracking Error ◽  
Cmos Technology ◽  
Current Mirror ◽  
Design Environment ◽  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
High Output

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

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