High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell

2019 ◽  
Vol 28 (08) ◽  
pp. 1950140
Author(s):  
Caffey ◽  
Rishikesh Pandey
Keyword(s):  
Supply Voltage ◽  
Tracking Error ◽  
Cmos Technology ◽  
Current Mirror ◽  
Design Environment ◽  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
High Output

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

A Class-AB Bulk-Driven Amplifier with Enhanced Transconductance Using Quasi-Floating Gate Method

2018 ◽  
Vol 27 (09) ◽  
pp. 1850137
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Cmos Technology ◽  
Floating Gate ◽  
Common Source ◽  
Slew Rate ◽  
Power Budget ◽  
Ultra Low Power ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Adaptive Biasing

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.

scholarly journals Class AB flipped voltage follower with very low output resistance and no additional power

2018 ◽  
Vol 15 (4) ◽  
pp. 20171170-20171170 ◽  
Author(s):  
Ivan Padilla-Cantoya ◽  
Jesus E. Molinar-Solis ◽  
Jaime Ramirez-Angulo
Keyword(s):  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower

scholarly journals K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 890
Author(s):  
Kyu-Jin Choi ◽  
Jae-Hyun Park ◽  
Seong-Kyun Kim ◽  
Byung-Sung Kim
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Output Resistance ◽  
Power Added Efficiency ◽  
High Output ◽  
K Band

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

scholarly journals A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

2017 ◽  
Vol 37 (2) ◽  
pp. 82-88 ◽  
Author(s):  
Juan Jesus Ocampo-Hidalgo ◽  
Iván Vázquez-Álvarez ◽  
Sergio Sandoval-Perez ◽  
Rodolfo Garcia-Lozano ◽  
Marco Gurrola-Navarro ◽  
...  
Keyword(s):  
Low Voltage ◽  
Harmonic Distortion ◽  
Main Idea ◽  
Cmos Technology ◽  
Floating Gate ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Micro Power ◽  
Voltage Follower ◽  
Analog Voltage

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

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