High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower

2019 ◽  
Vol 47 (4) ◽  
pp. 499-512 ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Alessandro Trifiletti
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.


2013 ◽  
Vol 44 (10) ◽  
pp. 930-940 ◽  
Author(s):  
C. Muñiz-Montero ◽  
L.A. Sánchez-Gaspariano ◽  
J.J. Camacho-Escoto ◽  
L.A. Villa-Vargas ◽  
H. Molina-Lozano ◽  
...  

2000 ◽  
Vol 36 (17) ◽  
pp. 1439 ◽  
Author(s):  
H. Elwan ◽  
W. Gao ◽  
R. Sadkowski ◽  
M. Ismail

2018 ◽  
Vol 27 (09) ◽  
pp. 1850137
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.


2018 ◽  
Vol 15 (4) ◽  
pp. 20171170-20171170 ◽  
Author(s):  
Ivan Padilla-Cantoya ◽  
Jesus E. Molinar-Solis ◽  
Jaime Ramirez-Angulo

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