A low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell

Integration ◽  
2021 ◽  
Author(s):  
Caffey Jindal ◽  
Rishikesh Pandey
2018 ◽  
Vol 15 (4) ◽  
pp. 20171170-20171170 ◽  
Author(s):  
Ivan Padilla-Cantoya ◽  
Jesus E. Molinar-Solis ◽  
Jaime Ramirez-Angulo

2019 ◽  
Vol 28 (08) ◽  
pp. 1950140
Author(s):  
Caffey ◽  
Rishikesh Pandey

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.


2013 ◽  
Vol 44 (10) ◽  
pp. 930-940 ◽  
Author(s):  
C. Muñiz-Montero ◽  
L.A. Sánchez-Gaspariano ◽  
J.J. Camacho-Escoto ◽  
L.A. Villa-Vargas ◽  
H. Molina-Lozano ◽  
...  

2018 ◽  
Vol 27 (09) ◽  
pp. 1850137
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.


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