InSb/Si Heterojunction-Based Tunnelling Field-Effect Transistor with Enhanced Drive Current and Steep Switching

Author(s):  
Sukanta Kumar Swain ◽  
Nishit Malviya ◽  
Sangeeta Singh ◽  
Shashi Kant Sharma
Nano Letters ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1758-1764
Author(s):  
Zhaowu Tang ◽  
Chunsen Liu ◽  
Xiaohe Huang ◽  
Senfeng Zeng ◽  
Liwei Liu ◽  
...  

Author(s):  
Ajay Kumar Singh ◽  
Tan Chun Fui

Background: Power reduction is a severe design concern for submicron logic circuits, which can be achieved by scaling the supply voltage. Modern Field Effect Transistor (FET) circuits require at least 60 mV of gate voltage for a better current drive at room temperature. The tunnel Field Effect Transistor (TFET) is a leading future device due to its steep subthreshold swing (SS), making its ideal device at a low power supply. Steep switching TFET can extend the supply voltage scaling with improved energy efficiency for digital and analog applications. These devices suffer from a sizeable ambipolar current, which cannot be reduced using Dual Metal Gate (DMG) alone. Gate dielectric materials play a crucial role in suppressing the ambipolar current. Objective: This paper presents a new structure known as triple-gate-dielectric (DM_TGD) TFET, which combines the dielectric and work function engineering to solve these problems. Method: The proposed structure uses DMG with three dielectric gate materials titanium oxide (TiO2), aluminum oxide (Al2O3), and silicon dioxide (SiO2). The high dielectric material alone as gate oxide increases the fringing fields, which results in higher gate capacitance. This structure has been simulated using 2-D ATLAS simulator in terms of drive current (Ion), ambipolar current (Iamb) and transconductance (gm). Results: The device offers better gm, lower SS, lower leakage and larger drive currents due to weaker insulating barriers at the tunneling junction. Also, higher effective dielectric constant gives better gate coupling and lower trap density. Conclusion: The proposed structure suppresses the ambipolar current and enhance the drive current with reduced SCEs.


2018 ◽  
Vol 6 ◽  
pp. 721-725 ◽  
Author(s):  
Woojin Park ◽  
Amir N. Hanna ◽  
Arwa T. Kutbee ◽  
Muhammad Mustafa Hussain

2021 ◽  
Author(s):  
Kumari Nibha Priyadarshani ◽  
Sangeeta Singh ◽  
Kunal Singh

Abstract Ge-source dopingless tunnelling field effect transistor (Ge-source DLTFET) with the optimization of dielectric oxide thickness under the source and the gate contacts is proposed and investigated by calibrated 2D TCAD device simulation. As the structure is realized using dopingless technique, this enables lower thermal budget, higher immunity towards the random dopant fluctuations (RDFs) effects and velocity degradation effects. The optimization of dielectric thickness has been done to tune the carrier concentrations induced in source and channel regions in order to improve the device performance. The drive current is magnificently enhanced along with ION/IOFF ratio, peak transconductance and ultra-steep subthreshold slope (SS) is reported for the optimized Si-DLTFET. In addition to this by deploying Ge-source instead of Si source in optimized Si-DLTFET increases ON current slightly and OFF current gets reduced by the order of two as compared to the optimized Si-DLTFET. This improves the ION/IOFF ratio,the reported drive current for Ge-source DLTFET is 5.1×10− 4 A/µm, along with ION/IOFF ratio as 1.54×1013, peak transconductance as 1.26 mS/µm and ultra-steep SS as 1.69 mV/decade. Further, the analog, RF and linearity performance parameters have also been investigated for both the structures and demonstrated notable improvement. The energy efficiency investigationreveals a significant reduction in energy-delay product. This paper indicates thepotentials of optimized Si-DLTFET and Ge-source DLTFET as promising candidates for low power analog and RF applications and Ge-source DLTFET hasbetter device dc performance.


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