First demonstration of robust tri-gate β-Ga2O3 nano-membrane field-effect transistors

Nano-membrane tri-gate β-gallium oxide (β-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between β-Ga2O3 and gate dielectric, atomic layer-deposited 15-nm-thick aluminum oxide (Al2O3) was utilized with Tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV/dec, high drain current (I DS) ON/OFF ratio of 1.5 × 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current–voltage (I–V) characteristics measured at temperatures up to 400 °C.

Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in-situ deposited Al2O3/Y2O3 as a gate dielectric

We have demonstrated a record low 85 mV/dec subthreshold slope (SS) at 300 K among the planar inversion-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). Our MOSFETs using in-situ deposited Al2O3/Y2O3 as a gate dielectric were fabricated with a self-aligned inversion-channel metal-gate-first process. The temperature-dependent transfer characteristics showed a linear reduction of SS versus temperature, with attainment of an SS of 22 mV/dec at 77 K; the value is comparable to that of the state-of-the-art InGaAs FinFET. The slope factor of SS with temperature (m) is 1.33, which is lower than those reported in the planar InGaAs MOSFETs.

Low Subthreshold Slope AlGaN/GaN MOS-HEMT with Spike-Annealed HfO2 Gate Dielectric

AlGaN/GaN metal-oxide semiconductor high electron mobility transistors (MOS-HEMTs) with undoped ferroelectric HfO2 have been investigated. Annealing is often a critical step for improving the quality of as-deposited amorphous gate oxides. Thermal treatment of HfO2 gate dielectric, however, is known to degrade the oxide/nitride interface due to the formation of Ga-containing oxide. In this work, the undoped HfO2 gate dielectric was spike-annealed at 600 °C after the film was deposited by atomic layer deposition to improve the ferroelectricity without degrading the interface. As a result, the subthreshold slope of AlGaN/GaN MOS-HEMTs close to 60 mV/dec and on/off ratio>109 were achieved. These results suggest optimizing the HfO2/nitride interface can be a critical step towards a low-loss high-power switching device.

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

Investigation on the interface trap characteristics in a p-channel GaN MOSFET through temperature-dependent subthreshold slope analysis

In this paper, a simple method based on subthreshold slopes was proposed to investigate the interface trap characteristics in a p-channel GaN MOSFET with a p-GaN/AlGaN/GaN structure on Si. The energy distribution of the interface trap density has been extracted from the analysis of the transfer characteristics in the subthreshold region of operation. The interface trap densities and respective energy distribution at both room temperature and 150 ℃ were also calculated from the ac conductance measurements at corresponding applied biases. Both characterization methods show similar results of trap densities and energy levels.

Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, ION of the order of 100 nA µm−2 and ION/IOFF > 104 at Vd = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.