Ana Isabela Araújo Cunha
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Antonio José Sobrinho De Sousa
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Edson Pinto Santana
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Robson Nunes De Lima
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Fabian Souza De Andrade
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This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.
New current‐mode RMS‐to‐DC converters and four‐quadrant multiplier/divider based on VDTA