A transistorized double time delay switch of high accuracy and reproducibility

1963 ◽  
Vol 8 (2) ◽  
pp. 321-323
Author(s):  
H. Kruijswijk ◽  
J.G. Pelle
Keyword(s):  
Time Delay ◽  
High Accuracy ◽  
Double Time

Compact Size Multi-Channel True Time Delay Moudle with High Accuracy

2018 ◽  
Author(s):  
Lizhena Zhang ◽  
Zhenhai Li ◽  
Kai Chen ◽  
Guilian Chen ◽  
Yong Zhao
Keyword(s):  
Time Delay ◽  
High Accuracy ◽  
True Time Delay ◽  
Compact Size ◽  
True Time

High Accuracy Time Delay Measurements for Band-Pass Signals

2013 ◽  
Vol 62 (11) ◽  
pp. 2998-3005 ◽  
Author(s):  
Yong Huang ◽  
Jingli Lin ◽  
Mohaned Giess
Keyword(s):  
Time Delay ◽  
High Accuracy ◽  
Band Pass

scholarly journals Tensor-Based Framework With Model Order Selection and High Accuracy Factor Decomposition for Time-Delay Estimation in Dynamic Multipath Scenarios

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 174931-174942
Author(s):  
Mateus Da Rosa Zanatta ◽  
Joao Paulo Carvalho Lustosa Da Costa ◽  
Felix Antreich ◽  
Martin Haardt ◽  
Gordon Elger ◽  
...  
Keyword(s):  
Time Delay ◽  
High Accuracy ◽  
Time Delay Estimation ◽  
Delay Estimation ◽  
Order Selection ◽  
Model Order Selection ◽  
Model Order ◽  
Factor Decomposition

scholarly journals Bifurcation Control in an Optimal Velocity Model via Double Time-Delay Feedback Method

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 216162-216175
Author(s):  
Weilin Ren ◽  
Rongjun Cheng ◽  
Hongxia Ge ◽  
Qi Wei
Keyword(s):  
Time Delay ◽  
Velocity Model ◽  
Bifurcation Control ◽  
Optimal Velocity ◽  
Optimal Velocity Model ◽  
Feedback Method ◽  
Double Time

Time Delay Model for SRAM Compiler

2013 ◽  
Vol 373-375 ◽  
pp. 1561-1566
Author(s):  
Qiang Song ◽  
Chun Yu Peng ◽  
Hong Gang Zhou ◽  
Shou Biao Tan
Keyword(s):  
Time Delay ◽  
Delay Time ◽  
High Accuracy ◽  
Cmos Process ◽  
Delay Model ◽  
Effective Time

In this paper, we introduced an effective time delay model for SRAM compiler, which represents an important performance of SRAM. Our method divide the delay time into several periods, including decoder delay, word line delay, bit line delay and SA delay. The theory is useful in predicting the delay time when the SRAM size is changed. Simulations by Hsim in 65nm CMOS process proves a high accuracy.

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