A scalable high-linearity two-step DTC-assisted voltage–to-time converter with rail-to-rail input-range for time-based circuits

In this paper, a novel and simple multi-bit quantizer based on the threshold inverter quantization (TIQ) approach is presented for use in sampled-data circuits. The key part is a front-end signal conditioning circuit with the aid of the interpolation technique that makes it possible to realize a rail-to-rail input range operation over the conventional threshold inverter-based quantizer circuits while maintaining the benefits of the TIQ structure without employing any analog-intensive circuits such as current sources or amplifiers, thus achieving a digital-compatible implementation. Simulation results in TSMC 90-nm CMOS technology at a power-supply voltage of 1[Formula: see text]V confirm the efficient performance of the proposed circuit.

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1-bit quantiser with rail to rail input range for sub-1 V modulators

Electronics Letters ◽

10.1049/el:20030588 ◽

2003 ◽

Vol 39 (12) ◽

pp. 894 ◽

Cited By ~ 38

Author(s):

M. Maymandi-Nejad ◽

M. Sachdev

Keyword(s):

Rail To Rail ◽

Input Range

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Low-Power ASK Detector for Low Modulation Indexes and Rail-to-Rail Input Range

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2015.2503651 ◽

2016 ◽

Vol 63 (5) ◽

pp. 458-462 ◽

Cited By ~ 5

Author(s):

Vincenzo Fiore ◽

Egidio Ragonese ◽

Giuseppe Palmisano

Keyword(s):

Low Power ◽

Rail To Rail ◽

Input Range

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A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.483.487 ◽

2011 ◽

Vol 483 ◽

pp. 487-491

Author(s):

Wei Ping Chen ◽

Tian Yang Wang ◽

Hong Lei Xu ◽

Xiao Wei Liu

Keyword(s):

Power Consumption ◽

Input Impedance ◽

Circuit Simulation ◽

Cmos Technology ◽

Analog Multiplier ◽

High Input ◽

High Linearity ◽

Novel Structure ◽

Input Range ◽

Four Quadrant

A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.

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