An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

2015 ◽  
Vol 62 (10) ◽  
pp. 2380-2390 ◽  
Author(s):  
Omar Abdelfattah ◽  
Gordon W. Roberts ◽  
Ishiang Shih ◽  
Yi-Chi Shih
2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.


2009 ◽  
Vol 61 (2) ◽  
pp. 181-189 ◽  
Author(s):  
Hamid Movahedian Attar ◽  
Mehrdad Sharif Bakhtiar

Author(s):  
M.F. Li ◽  
U. Dasgupta ◽  
X.W. Zhang ◽  
Yong Ching Lim

2008 ◽  
Vol 55 (12) ◽  
pp. 1229-1233 ◽  
Author(s):  
Jaime RÁmirez-Angulo ◽  
Sandhana Balasubramanian ◽  
Antonio J. LÓpez-Martin ◽  
RamÓn G. Carvajal

Author(s):  
C. Azcona ◽  
B. Calvo ◽  
N. Medrano ◽  
S. Celma

This work presents a low-power rail-to-rail temperature compensated voltage-to-frequency converter (VFC) which constitutes the last stage of a sensor read-out interface targeting wireless sensor networks (WSN) applications. These quasi-digital converters are now receiving great interest, since they combine the simplicity of analog devices with the accuracy and noise immunity proper to digital signal processing; besides, frequency output is directly driven to the embedded node microcontroller C, which next performs the A/D conversion using its internal timers. A first read-out interface prototype using low-voltage low-power commercial components shows that the VFC means 99 % of the total interface consumption in read-out mode. Further, existing CMOS VFCs in the form of ASICs have a rather limited input range and an unsuitable output frequency span for typical C clock frequencies used in WSN. Hence, a novel full custom VFC solution is needed, fullfilling the main requirements of rail-to-rail operation, to take advantage of the full supply voltage range to optimize the output frequency resolution, and low-power low-voltage operation to have a power supply compatible with conventional WSN batteries while maximizing the operating life of the sensor node. Experimental results for a 0.18–μm 1.2–V CMOS VFC implementation show for an input range of (0–1.2 V) an output frequency range of (0.1–1.0 MHz), adequate to digitize the signal with the direct counting method in the sensor node μC achieving 13 bits resolution. It has a power consumption of 60 μW (35 nW in sleep mode) and it is temperature insensitive for a temperature range of (-40, 120 ºC).


2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).


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