Corrigendum to “On the application of a unified adaptive filter theory in the performance prediction of adaptive filter algorithms” [Digital Signal Process. 19 (2009) 410–432]

2010 ◽  
Vol 20 (1) ◽  
pp. 301
Author(s):  
Mohammad Shams Esfand Abadi ◽  
John Håkon Husøy
2012 ◽  
Vol 198-199 ◽  
pp. 696-700
Author(s):  
Wen Liang Niu ◽  
Wen Zheng Li ◽  
Kai Shuang Yin

HW/SW (hardware/software) co-design method based on analysis and optimization of DFG (data flow graphic) model is introduced for SOPC (System on a Programmable Chip) used for digital instrument design in this paper. The method is based on the DFG model of the digital signal process algorithm and implemented with SOPC technology. The DFG model could help designer to divide the function into hardware and software respectively, therefore, the optimizing analysis at system level and circuit level of a SOPC used for portable logic analyzer shows that the DFG model is very useful for not only optimizing architecture and power consumption, but also HW/SW co-design.


2016 ◽  
Vol 693 ◽  
pp. 1517-1523
Author(s):  
Ping Lian ◽  
Xiu Wen Jin

The spectrum of the load component is retained and the spectrum of other components are eliminated by the identifying spectrum is processed with addition or subtraction in the frequency domain. The method avoids an error that Gibbs’ vibration is generated as the signals multiply each other in frequency domain is equivalent to the signals are convolution in time domain in the filtering. On the basis of Fourier transformation, the method only using addition or subtraction obtains useful frequency components. Compare with other processing methods, the processing result can satisfy the identifying requests. In practice, the method is simple and convenient and the operational error is less. It is a try for digital signal process.


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