scholarly journals Analysis of the aliasing effect caused in hardware-in-the-loop when reading PWM inputs of power converters

2022 ◽  
Vol 136 ◽  
pp. 107678
Author(s):  
Elyas Zamiri ◽  
Alberto Sanchez ◽  
María Sofía Martínez-García ◽  
Angel de Castro
Keyword(s):  
Power Converters ◽  
Hardware In The Loop

scholarly journals SHIL and DHIL Simulations of Nonlinear Control Methods Applied for Power Converters Using Embedded Systems

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 241 ◽  
Author(s):  
Arthur Rosa ◽  
Matheus Silva ◽  
Marcos Campos ◽  
Renato Santana ◽  
Welbert Rodrigues ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Nonlinear Control ◽  
Real Time ◽  
Digital Signal Processor ◽  
High Performance ◽  
Power Converters ◽  
Digital Signal ◽  
Simulation Method ◽  
Hardware In The Loop ◽  
Control Techniques

In this work, a new real-time Simulation method is designed for nonlinear control techniques applied to power converters. We propose two different implementations: in the first one (Single Hardware in The Loop: SHIL), both model and control laws are inserted in the same Digital Signal Processor (DSP), and in the second approach (Double Hardware in The Loop: DHIL), the equations are loaded in different embedded systems. With this methodology, linear and nonlinear control techniques can be designed and compared in a quick and cheap real-time realization of the proposed systems, ideal for both students and engineers who are interested in learning and validating converters performance. The methodology can be applied to buck, boost, buck-boost, flyback, SEPIC and 3-phase AC-DC boost converters showing that the new and high performance embedded systems can evaluate distinct nonlinear controllers. The approach is done using matlab-simulink over commodity Texas Instruments Digital Signal Processors (TI-DSPs). The main purpose is to demonstrate the feasibility of proposed real-time implementations without using expensive HIL systems such as Opal-RT and Typhoon-HL.

scholarly journals Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1527
Author(s):  
María Sofía Martínez-García ◽  
Angel de Castro ◽  
Alberto Sanchez ◽  
Javier Garrido
Keyword(s):  
Power Converters ◽  
Design Criterion ◽  
Feedback Signal ◽  
Hardware In The Loop ◽  
State Variables ◽  
Gate Arrays ◽  
State Variable ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Optimum Width

One of the main techniques for debugging power converters is hardware-in-the-loop (HIL), which is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common design platforms due to their acceleration capability. In this case, the widths of the signals have to be carefully chosen to optimize the area and speed. For this purpose, fixed-point arithmetic is one of the best options because although the design time is high, it allows the personalization of the number of bits in every signal. The representation of state variables in power converters has been previously studied, however other signals, such as feedback signals, can also have a big influence because they transmit the value of one state variable to the rest, and vice versa. This paper presents an analysis of the number of bits in the feedback signals of a boost converter, but the conclusions can be extended to other power converters. The purpose of this work is to study how many bits are necessary in order to avoid the loss of information, but also without wasting bits. Errors of the state variables are obtained with different sizes of feedback signals. These show that the errors in each state variable have similar patterns. When the number of bits increases, the error decreases down to a certain number of bits, where an almost constant error appears. However, when the bits decrease, the error increases linearly. Furthermore, the results show that there is a direct relation between the number of bits in feedback signals and the inputs of the converter in the global error. Finally, a design criterion is given to choose the optimum width for each feedback signal, without wasting bits.

Real-Time FPGA-Based Hardware-in-the-Loop Simulation Test Bench Applied to Multiple-Output Power Converters

2011 ◽  
Vol 47 (2) ◽  
pp. 853-860 ◽  
Author(s):  
Oscar Lucia ◽  
Isidro Urriza ◽  
Luis A. Barragan ◽  
Denis Navarro ◽  
Oscar Jimenez ◽  
...  
Keyword(s):  
Real Time ◽  
Output Power ◽  
Test Bench ◽  
Power Converters ◽  
Hardware In The Loop ◽  
Simulation Test

scholarly journals Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1952
Author(s):  
Eva M. Cirugeda-Roldán ◽  
María Sofía Martínez-García ◽  
Alberto Sanchez ◽  
Angel de Castro
Keyword(s):  
High Speed ◽  
Power Converters ◽  
Low Cost ◽  
Hardware In The Loop ◽  
Main Design ◽  
Gate Arrays ◽  
The World ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Area Optimization

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.

scholarly journals FPGA based Hardware-in-the-Loop Simulation for Digital Control of Power Converters using VHDL-AMS

2018 ◽  
Vol 9 (12) ◽  
Author(s):  
Abdelouahab Djoubair Benhamadouche ◽  
Adel Ballouti ◽  
Farid Djahli ◽  
Abdeslem Sahli
Keyword(s):  
Digital Control ◽  
Power Converters ◽  
Hardware In The Loop

scholarly journals Emulator Based on Switching Functions for a Dual Interleaved Buck-Boost Converter

2019 ◽  
Vol 2019 ◽  
pp. 1-10
Author(s):  
Marco Antonio Sánchez Vázquez ◽  
Ismael Araujo-Vargas ◽  
Kevin Cano-Pulido
Keyword(s):  
Complex System ◽  
Field Programmable Gate Array ◽  
Power Converters ◽  
Piecewise Linear ◽  
Euler Method ◽  
Hardware In The Loop ◽  
Switching Cycle ◽  
Hybrid Power ◽  
Switching Functions ◽  
Field Programmable

Under the unavailability of some components of a complex system, the Hardware In the Loop (HIL) tool allows the emulation of other subsystems. When these devices are not available, a customized emulator can be developed based on the Piecewise Linear Model (PWLM) and a numerical method for solving the differential equations system. However, these implementations require the use of a Field Programmable Gate Array (FPGA) with extensive hardware resources. In this article we propose the use of switching functions for the modeling of power converters of a Hybrid Power System (HPS), allowing the reduction of hardware resources of the FPGA, and the number of steps per switching cycle is increased. The results are compared with SABER simulations and a PWLM evaluated with the Euler method.

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