switching cycle
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2021 ◽  
Author(s):  
Boran Fan ◽  
Jun Wang ◽  
Yu Rong ◽  
Vladimir Mitrovic ◽  
Jianghui Yu ◽  
...  

2021 ◽  
Vol 11 (13) ◽  
pp. 5901
Author(s):  
Qingyang Tan ◽  
Liangzong He

An improved modulation strategy based on minimum energy storage for DC-link capacitance reduction in a six-switch AC-AC converter is proposed. The proposed modulation strategy enables the energy on the capacitor to accumulate and release twice each in a complete switching cycle, achieving the effect of “fast charging and discharging”. Meanwhile, the inversion and rectification are modulated synchronously. Hence, there is minimum energy stored in the DC-link capacitor. Then, the time average modeling analysis is presented to take insight analysis. When there is the same voltage ripples constraint on the DC side for the conventional and improved modulation strategies, the six-switch converter under the improved modulation strategy has the much less capacitance value of the storage capacitor and even realizes non-electrolytic capacitance. Therefore, improving the system efficiency, power density, and output waveform quality and extending the system life can be achieved. The operation principle and modulation strategy are discussed in detail. Finally, the simulation model and experimental prototype are built to verify effectiveness of the topology and correctness of the proposed six-switch AC-AC converter modulation strategy.


Energies ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 1112
Author(s):  
Qixing Wu ◽  
Mingyu Gao ◽  
Huipin Lin ◽  
Zhekang Dong

In the application of a long series battery group, an inter-pack imbalance is inevitable. No intra-pack cell equalizer can prevent pack-level over-discharge. A bimodal, multichannel battery pack equalizer based on a quasi-resonant, two-transistor forward converter is proposed to solve this problem and achieve a tradeoff between balancing efficiency and speed. This equalizer has two modes: pack-to-pack-group and pack-to-any-pack (P2PG&AP) mode and direct-pack-to-pack (DP2P) mode. In P2PG&AP mode, this equalizer can realize the full-switching-cycle (FSC) equalization through three balancing channels, and transfer energy from any pack to both the whole group and any pack inside the group. In addition, it can effectively clamp the transformer-induced voltage using a secondary side two-transistor magnetic reset structure (STMR) and reduce the total turns of transformer coil from 70 to 50 turns via a secondary side boost converter (SBC). In DP2P mode, this equalizer can realize zero voltage gap (ZVG) equalization. A prototype was tested at different switching frequencies and LC values to validate the theoretical analysis and optimize the bimodal hybrid operation. Experiment results including higher than 89.66% efficiency and minute-level balancing time under different pack voltage distributions show that the proposed topology demonstrates excellent balancing performance.


2021 ◽  
Vol 57 (32) ◽  
pp. 3913-3916
Author(s):  
José García-Calvo ◽  
Javier López-Andarias ◽  
Naomi Sakai ◽  
Stefan Matile

The need of the primary dipole of flipper mechanophores has often been claimed but never confirmed. Here, a complete sulfur switching cycle is realized to prove that the central paradigm of fluorescent membrane tension probes is correct.


Energies ◽  
2020 ◽  
Vol 13 (6) ◽  
pp. 1439
Author(s):  
Dorin Petreus ◽  
Radu Etz ◽  
Toma Patarau ◽  
Ionut Ciocan

A phase-shift full bridge converter is analyzed in detail in continuous conduction mode for one switching cycle for both the leading and lagging legs of the primary bridge. The objective of the study is to determine how the stray capacitance of the transformer, and the capacitances of the diodes in the bridge rectifier affect the converter functionality. Starting from some experimental results, Laplace equivalent circuit models and describing equations are derived for each significant time interval during the switching cycle and are validated through simulations and experimental measurements. The resulting equations are of great interest in the high-power density domain because they can be used to design a clamping circuit for the output rectifier bridge accurately.


Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 489 ◽  
Author(s):  
Guohua Li ◽  
Chunwu Liu ◽  
Zhenfang Fu ◽  
Yufeng Wang

In the existing random pule width modulation (RPWM) selective harmonic elimination methods, the formula of switching cycle TN+1 is complex, and the duty ratio DN+1 of the next switching cycle needs to be calculated in advance. However, in the case of unknown TN+1, DN+1 is also difficult to calculate accurately, and the two parameters are based on each other. A novel selective harmonic elimination method in RPWM is proposed in this paper. The PWM voltage pulse is placed at the back of the switch cycle, which simplifies the formula of the switch cycle TN+1 and eliminates the need to calculate the duty ratio DN+1. Two kinds of RPWM selective harmonic elimination ideas are summarized. The general formulas of the switch cycle, the effective random number k, and the upper and lower limits of switch frequency corresponding to k are derived. The spectrum shaping of inverter output voltage can be realized without using digital filter in this method. Simple algorithm, small calculation and easy implementation are characteristics of the proposed method. The simulation and experimental results confirm the ability of the proposed method for reducing harmonics at the specific frequency in power spectral density (PSD).


2019 ◽  
Vol 2019 ◽  
pp. 1-10
Author(s):  
Marco Antonio Sánchez Vázquez ◽  
Ismael Araujo-Vargas ◽  
Kevin Cano-Pulido

Under the unavailability of some components of a complex system, the Hardware In the Loop (HIL) tool allows the emulation of other subsystems. When these devices are not available, a customized emulator can be developed based on the Piecewise Linear Model (PWLM) and a numerical method for solving the differential equations system. However, these implementations require the use of a Field Programmable Gate Array (FPGA) with extensive hardware resources. In this article we propose the use of switching functions for the modeling of power converters of a Hybrid Power System (HPS), allowing the reduction of hardware resources of the FPGA, and the number of steps per switching cycle is increased. The results are compared with SABER simulations and a PWLM evaluated with the Euler method.


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