Two hardware implementations for modular multiplication in the AMNS: Sequential and semi-parallel

2021 ◽  
Vol 58 ◽  
pp. 102770
Author(s):  
Asma Chaouch ◽  
Laurent-Stéphane Didier ◽  
Fangan Yssouf Dosso ◽  
Nadia El Mrabet ◽  
Belgacem Bouallegue ◽  
...  
2017 ◽  
Vol E100.B (5) ◽  
pp. 680-690 ◽  
Author(s):  
Yang LI ◽  
Jinlin WANG ◽  
Xuewen ZENG ◽  
Xiaozhou YE

2021 ◽  
Author(s):  
Tao Zeng ◽  
Zhi Yang ◽  
Jiabing Liang ◽  
Ya Lin ◽  
Yankun Cheng ◽  
...  

Memristive devices are widely recognized as promising hardware implementations of neuromorphic computing. Herein, a flexible and transparent memristive synapse based on polyvinylpyrrolidone (PVP)/N-doped carbon quantum dot (NCQD) nanocomposites through regulating...


2021 ◽  
pp. 000370282110133
Author(s):  
Rohit Bhargava ◽  
Yamuna Dilip Phal ◽  
Kevin Yeh

Discrete frequency infrared (DFIR) chemical imaging is transforming the practice of microspectroscopy by enabling a diversity of instrumentation and new measurement capabilities. While a variety of hardware implementations have been realized, considerations in the design of all-IR microscopes have not yet been compiled. Here we describe the evolution of IR microscopes, provide rationales for design choices, and the major considerations for each optical component that together comprise an imaging system. We analyze design choices in illustrative examples that use these components to optimize performance, under their particular constraints. We then summarize a framework to assess the factors that determine an instrument’s performance mathematically. Finally, we summarize the design and analysis approach by enumerating performance figures of merit for spectroscopic imaging data that can be used to evaluate the capabilities of imaging systems or suitability for specific intended applications. Together, the presented concepts and examples should aid in understanding available instrument configurations, while guiding innovations in design of the next generation of IR chemical imaging spectrometers.


Author(s):  
Johannes Mittmann ◽  
Werner Schindler

AbstractMontgomery’s and Barrett’s modular multiplication algorithms are widely used in modular exponentiation algorithms, e.g. to compute RSA or ECC operations. While Montgomery’s multiplication algorithm has been studied extensively in the literature and many side-channel attacks have been detected, to our best knowledge no thorough analysis exists for Barrett’s multiplication algorithm. This article closes this gap. For both Montgomery’s and Barrett’s multiplication algorithm, differences of the execution times are caused by conditional integer subtractions, so-called extra reductions. Barrett’s multiplication algorithm allows even two extra reductions, and this feature increases the mathematical difficulties significantly. We formulate and analyse a two-dimensional Markov process, from which we deduce relevant stochastic properties of Barrett’s multiplication algorithm within modular exponentiation algorithms. This allows to transfer the timing attacks and local timing attacks (where a second side-channel attack exhibits the execution times of the particular modular squarings and multiplications) on Montgomery’s multiplication algorithm to attacks on Barrett’s algorithm. However, there are also differences. Barrett’s multiplication algorithm requires additional attack substeps, and the attack efficiency is much more sensitive to variations of the parameters. We treat timing attacks on RSA with CRT, on RSA without CRT, and on Diffie–Hellman, as well as local timing attacks against these algorithms in the presence of basis blinding. Experiments confirm our theoretical results.


2021 ◽  
Vol 11 (2) ◽  
pp. 23
Author(s):  
Duy-Anh Nguyen ◽  
Xuan-Tu Tran ◽  
Francesca Iacopi

Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.


2021 ◽  
Vol 21 (3) ◽  
pp. 1-20
Author(s):  
Mohamad Ali Mehrabi ◽  
Naila Mukhtar ◽  
Alireza Jolfaei

Many Internet of Things applications in smart cities use elliptic-curve cryptosystems due to their efficiency compared to other well-known public-key cryptosystems such as RSA. One of the important components of an elliptic-curve-based cryptosystem is the elliptic-curve point multiplication which has been shown to be vulnerable to various types of side-channel attacks. Recently, substantial progress has been made in applying deep learning to side-channel attacks. Conceptually, the idea is to monitor a core while it is running encryption for information leakage of a certain kind, for example, power consumption. The knowledge of the underlying encryption algorithm can be used to train a model to recognise the key used for encryption. The model is then applied to traces gathered from the crypto core in order to recover the encryption key. In this article, we propose an RNS GLV elliptic curve cryptography core which is immune to machine learning and deep learning based side-channel attacks. The experimental analysis confirms the proposed crypto core does not leak any information about the private key and therefore it is suitable for hardware implementations.


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