Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells

2016 ◽  
Vol 16 ◽  
pp. 8-15 ◽  
Author(s):  
Firdous Ahmad ◽  
Ghulam Mohiuddin Bhat ◽  
Hossein Khademolhosseini ◽  
Saeid Azimi ◽  
Shaahin Angizi ◽  
...  
2018 ◽  
Vol 9 (4) ◽  
pp. 2641-2648 ◽  
Author(s):  
Md. Abdullah-Al-Shafi ◽  
Ali Newaz Bahar ◽  
Md. Ahsan Habib ◽  
Mohammad Maksudur Rahman Bhuiyan ◽  
Firdous Ahmad ◽  
...  

2021 ◽  
Author(s):  
Mukesh Patidar ◽  
Namit Gupta

Abstract Quantum-dot cellular automata (QCA) are a novel dominant transistor-less computational nanotechnology. It is an appropriate candidate for the upcoming generation of quantum computational nano-electronics technology. The main objective of this research work is to present a QCA reversible logic circuits design such as the Toffoli gate (TG) and Peres gate (PG) and do the analysis of different parameters. In this paper, we propose a single layer coplanar method to solve this physical layout design and synchronization problem. The presented reversible logic gate (RLG) layout designs are implemented by Bijection functional algorithm for reduction of the number of QCA (quantum) cells, latency, and minimum design area. Also, the Optimized energy dissipation and effect of temperature on output polarization cell, of the proposed structure have been checked successfully using the tool QD-E (Energy) tool. The proposed QCA design has been verified by QCADesigner-E 2.2 tool using a bistable approximation and coherence vector engine. Finally, comparisons have been proposed RLG-TG and RLG-PG designs with the existing QCA design.


2021 ◽  
Vol 11 (18) ◽  
pp. 8717
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar

One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite and computing circuit, performing both the addition and the subtraction processes, is of particular importance. This paper implements three new Full Adder/Subtractor circuits with the lowest number of cells, lowest area, lowest latency, and a coplanar (single-layer) circuit design, as was shown by comparing the results obtained with those of the best previous works on this topic.


2014 ◽  
Vol 2014 (1) ◽  
pp. 37-44 ◽  
Author(s):  
Arighna Sarkar ◽  
◽  
Debarka Mukhopadhyay ◽  

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