scholarly journals Design and Implementation of Novel Efficient Full Adder/Subtractor Circuits Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (18) ◽  
pp. 8717
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Single Layer ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
Nanoscale Level

One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite and computing circuit, performing both the addition and the subtraction processes, is of particular importance. This paper implements three new Full Adder/Subtractor circuits with the lowest number of cells, lowest area, lowest latency, and a coplanar (single-layer) circuit design, as was shown by comparing the results obtained with those of the best previous works on this topic.

scholarly journals Design of Efficient Full Adder in Quantum-Dot Cellular Automata

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Bibhash Sen ◽  
Ayush Rajoria ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Design ◽  
Majority Gate ◽  
Feature Size ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

scholarly journals Optimum multiplexer design in quantum-dot cellular automata

2020 ◽  
Vol 17 (1) ◽  
pp. 148 ◽  
Author(s):  
Esam AlKaldy ◽  
Ali H Majeed ◽  
Mohd Shamian Zainal ◽  
Danial MD Nor
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Boolean Function ◽  
High Speed ◽  
Building Blocks ◽  
Cmos Technology ◽  
Quantum Dot Cellular Automata ◽  
Quantum Technology ◽  
Logical Functions ◽  
Novel Design

<p>Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as high speed, small size, and low power consumption. QCA has two main building blocks (majority gate and inverter) used for design any Boolean function. QCA also has an inherent capability that used to design many important gates such as XOR and Multiplexer in optimal form without following any Boolean function. This paper presents a novel design 2:1 QCA-Multiplexer in two forms. The proposed design is very simple, highly efficient and can be used to produce many logical functions. The proposed design output comes from the inherent capabilities of quantum technology. New 4:1 QCA-Multiplexer has been built using the proposed structure. The output waveforms showed the wonderful performance of the proposed design in terms of the number of cells, area, and latency.</p>

scholarly journals Design of Coplanar Circuit Switching Network in Quantum Dot Cellular Automata

2019 ◽  
Vol 8 (4) ◽  
pp. 10611-10619
Keyword(s):  
Communication Network ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Reducing Power ◽  
Building Blocks ◽  
Cmos Technology ◽  
Switching Network ◽  
Circuit Switching ◽  
Quantum Dot Cellular Automata ◽  
Crossbar Switch

Quantum dot Cellular Automata (QCA) is the alternative technology to the classic CMOS technology since it is going to attain a road block in reducing power consumption and increase speed of the digital circuits. Circuit switching network is the basic component in order to transmit input signal among the different users within the communication network. A novel crossbar switch is proposed in this paper to design this communication network. The basic building blocks of the proposed circuit Switching network are Crossbar switch, Multiplexer and Demultiplexer. Multilayer QCA cells are almost impossible when compared to the fabrication feasibility of the single layer design. So this design is achieved in single layer.Circuit switching network is designed and compared with existing one using QCA Designer2.0.3.The designs are verified through matching up with truth tables.

An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder

2015 ◽  
Vol 11 (2) ◽  
pp. 173-180 ◽  
Author(s):  
Shaahin Angizi ◽  
Fahimeh Danehdaran ◽  
Soheil Sarmadi ◽  
Shadi Sheikhfaal ◽  
Nader Bagherzadeh ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Full Adder ◽  
Low Complexity ◽  
Quantum Dot Cellular Automata ◽  
Ultra High Speed

scholarly journals Next Generation Computing Using Quantum Dot Cellular Automata Nano Technology, New Promising Alternative to CMOS

2019 ◽  
Vol 8 (S3) ◽  
pp. 19-24
Author(s):  
Singathala Guru Viswadha
Keyword(s):  
Quantum Dots ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Building Blocks ◽  
Cmos Technology ◽  
Electronic Interaction ◽  
Physical Point ◽  
Promising Alternative ◽  
Processing Technologies ◽  
Quantum Dot Cellular Automata

CMOS technology is one of the most popular technology in the computer chip design industry and broadly used today to form integrated circuits in numerous and varied applications and it has transformed the field of electronics. Over the time the design methodologies and processing technologies of CMOS devices have greatest activity with the Moore’s law. Now CMOS technology has to face challenges to survive through the submicron ranges. The scaling in CMOS has reached higher limit, not only from technological and Physical point of view but also from economical and material aspects. This concept inspires the researches to look for new alternatives to CMOS which gives better performance and power consumption. One of the alternative technologies to digital designing in CMOS is the Quantum dot Cellular Automata (QCA). QCA is a technology it works on Electronic interaction between the cells. The QCA cell basically consists of Quantum dots separated by certain distance. The transmission of information done via the interaction between the Electrons present in these quantum dots. In this paper the limitations to CMOS in submicron range and concepts for designing in QCA have been discussed and also the building blocks are explained using QCA designer implementations with focus on cell interaction and clocking mechanism.

scholarly journals Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (24) ◽  
pp. 12157
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar ◽  
Khan A. Wahid
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gate ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Xor Gate ◽  
Design Complexity ◽  
Quantum Dot Cellular Automata

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

2020 ◽  
Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Quantum Dot Cellular Automata ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Area Efficient
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