Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Testing of components at higher-than-nominal stress level provides an effective way of reducing the required testing effort for system reliability assessment. Due to various reasons, not all components are directly testable in practice. The missing information of untestable components poses significant challenges to the accurate evaluation of system reliability. This paper proposes a sequential accelerated life testing (SALT) design framework for system reliability assessment of systems with untestable components. In the proposed framework, system-level tests are employed in conjunction with component-level tests to effectively reduce the uncertainty in the system reliability evaluation. To minimize the number of system-level tests, which are much more expensive than the component-level tests, the accelerated life testing (ALT) design is performed sequentially. In each design cycle, testing resources are allocated to component-level or system-level tests according to the uncertainty analysis from system reliability evaluation. The component-level or system-level testing information obtained from the optimized testing plans is then aggregated to obtain the overall system reliability estimate using Bayesian methods. The aggregation of component-level and system-level testing information allows for an effective uncertainty reduction in the system reliability evaluation. Results of two numerical examples demonstrate the effectiveness of the proposed method.

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Cross-layer power management in wireless networks and consequences on system-level architecture

Signal Processing ◽

10.1016/j.sigpro.2005.09.035 ◽

2006 ◽

Vol 86 (8) ◽

pp. 1792-1803 ◽

Cited By ~ 11

Author(s):

Bruno Bougard ◽

Sofie Pollin ◽

Antoine Dejonghe ◽

Francky Catthoor ◽

Wim Dehaene

Keyword(s):

Wireless Networks ◽

Power Management ◽

System Level ◽

Cross Layer

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An efficient reliability evaluation approach for system-level design of embedded systems

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810317 ◽

2009 ◽

Cited By ~ 1

Author(s):

Adeel Israr ◽

Abdulhadi Shoufan ◽

Sorin A. Huss

Keyword(s):

Embedded Systems ◽

Reliability Evaluation ◽

System Level ◽

System Level Design ◽

Evaluation Approach ◽

Level Design

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Mixed Signal System Level Cross Layer Adaptation for Variability and Workload: A Pilot Study

2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop ◽

10.1109/ims3tw.2011.26 ◽

2011 ◽

Author(s):

Shreyas Sen ◽

Jayaram Natarajan ◽

Joshua W. Wells ◽

Abhijit Chatterjee

Keyword(s):

Pilot Study ◽

System Level ◽

Cross Layer ◽

Signal System ◽

Mixed Signal

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Where to go from here? New cross layer techniques for LTE Turbo-Code decoding at high code rates

Advances in Radio Science ◽

10.5194/ars-16-77-2018 ◽

2018 ◽

Vol 16 ◽

pp. 77-87 ◽

Cited By ~ 1

Author(s):

Stefan Weithoffer ◽

Norbert Wehn

Keyword(s):

Turbo Codes ◽

State Of The Art ◽

Turbo Code ◽

System Level ◽

Cross Layer ◽

High Area ◽

Wide Range ◽

Block Level ◽

Hardware Architectures ◽

Block Sizes

Abstract. The wide range of code rates and code block sizes supported by todays wireless communication standards, together with the requirement for a throughput in the order of Gbps, necessitates sophisticated and highly parallel channel decoder architectures. Code rates specified in the LTE standard, which uses Turbo-Codes, range up to r=0.94 to maximize the information throughput by transmitting only a minimum amount of parity information, which negatively impacts the error correcting performance. This especially holds for highly parallel hardware architectures. Therefore, the error correcting performance must be traded-off against the degree of parallel processing. State-of-the-art Turbo-Code decoder hardware architectures are optimized on code block level to alleviate this trade-off. In this paper, we follow a cross-layer approach by combining system level knowledge about the rate-matching and the transport block structure in LTE with the bit-level technique of on-the-fly CRC calculation. Thereby, our proposed Turbo-Code decoder hardware architecture achieves coding gains of 0.4–1.8 dB compared to state-of-the-art accross a wide range of code block sizes. For the fully LTE compatible Turbo-Code decoder, we demonstrate a negligible hardware overhead and a resulting high area and energy efficiency and give post place and route synthesis numbers.

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Reliability Evaluation of Bicube-Based Multiprocessor System under the g-Good-Neighbor Restriction

Parallel Processing Letters ◽

10.1142/s0129626421500183 ◽

2021 ◽

Author(s):

Jiafei Liu ◽

Shuming Zhou ◽

Eddie Cheng ◽

Gaolin Chen ◽

Min Li

Keyword(s):

Cloud Computing ◽

Reliability Evaluation ◽

Big Data Analysis ◽

System Level ◽

Multiprocessor System ◽

Multiprocessor Systems ◽

Novel Variant ◽

Neighbor Connectivity ◽

Good Neighbor ◽

Primary Strategy

Multiprocessor systems are commonly deployed for big data analysis because of evolution in technologies such as cloud computing, IoT, social network and so on. Reliability evaluation is of significant importance for maintenance and improvement of fault tolerance for multiprocessor systems, and system-level diagnosis is a primary strategy to identify the faulty processors in the systems. In this paper, we first determine the [Formula: see text]-good-neighbor connectivity of the [Formula: see text]-dimensional Bicube-based multiprocessor system [Formula: see text], a novel variant of hypercube. Besides, we establish the [Formula: see text]-good-neighbor diagnosability of the Bicube-based multiprocessor system [Formula: see text] under the PMC and MM* models.

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