Impact of gate-to-source/drain misalignments on source-side injection Schottky barrier charge-trapping memory cells evaluated using numerical programming-trapping iterations

2017 ◽  
Vol 74 ◽  
pp. 9-14 ◽  
Author(s):  
Chun-Hsing Shih ◽  
Yen-Hsiang Lo ◽  
Yu-Hsuan Chen ◽  
Jr-Jie Tsai
2008 ◽  
Vol 92 (13) ◽  
pp. 133506 ◽  
Author(s):  
C. A. Kleint ◽  
T. Mueller ◽  
S. Teichert ◽  
C. Fitz ◽  
N. Nagel ◽  
...  

Author(s):  
Yu-Hsuan Chen ◽  
Chun-Hsing Shih ◽  
Hung-Jin Teng ◽  
Chenhsin Lien

2007 ◽  
Vol 997 ◽  
Author(s):  
Torsten Mueller ◽  
C. Kleint ◽  
C. Fitz ◽  
M. Isler ◽  
S. Riedel ◽  
...  

AbstractA 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.


2014 ◽  
Vol 563 ◽  
pp. 6-9 ◽  
Author(s):  
Zheng-Yi Cao ◽  
Ai-Dong Li ◽  
Xin Li ◽  
Yan-Qiang Cao ◽  
Di Wu

2006 ◽  
Vol 45 (4B) ◽  
pp. 3179-3184
Author(s):  
Lei Sun ◽  
Liyang Pan ◽  
Huiqing Pang ◽  
Ying Zeng ◽  
Zhaojian Zhang ◽  
...  

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