Recharging process of commercial floating-gate MOS transistor in dosimetry application

This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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A floating gate method for MOS transistor gate capacitance and Leff measurements and its implementation in a parametric test

Proceedings of the 1989 International Conference on Microelectronic Test Structures ◽

10.1109/icmts.1989.39275 ◽

2003 ◽

Author(s):

R. Kazerounian ◽

A. Singh ◽

B. Eltan

Keyword(s):

Floating Gate ◽

Parametric Test ◽

Mos Transistor ◽

Gate Capacitance

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A true single-phase clocked full-adder using floating-gate MOS transistor

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2014.7021589 ◽

2014 ◽

Author(s):

Guoqiang Hang ◽

Xiaohui Hu ◽

Danyan Zhang ◽

Yang Yang ◽

Jianzhong Wu

Keyword(s):

Single Phase ◽

Full Adder ◽

Floating Gate ◽

Mos Transistor

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Surface micromachining of a micro electromechanical inertial transducer based on commercially available Floating Gate Transistor technology

Superficies y Vacío ◽

10.47566/2018_syv31_1-030048 ◽

2018 ◽

Vol 31 (3) ◽

pp. 48-51

Author(s):

Griselda Stephany Abarca-Jiménez ◽

Gabriel Romero-Paredes Rubio ◽

Mario Alfredo Reyes-Barranca ◽

Miguel Ángel Alemán-Arce ◽

Jacobo Esteban Munguía-Cervantes ◽

...

Keyword(s):

Inertial Sensor ◽

Sacrificial Layer ◽

Cmos Technology ◽

Floating Gate ◽

Surface Micromachining ◽

Design Rules ◽

Fully Integrated ◽

Mos Transistor ◽

Processing Step ◽

Floating Gate Transistor

This work presents the results of different surface micromachining processes done on a chip from On Semiconductor 0.5 µm commercially available CMOS technology. The intended objective is to fabricate a MEMS inertial transducer in a monolithic substrate, as the electronics for signal processing are based on a Floating Gate MOS transistor, fully integrated in the electromechanical structure. According to the available layers and design rules from the foundry, an inertial sensor chip was designed and fabricated, except the last post–processing step, i.e., the removal of the sacrificial layer and thus releasing the inertial structure based on a surface micromachining process, allowing the completed device to behave as designed.

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