Very low voltage operational amplifiers using floating gate MOS transistor

Author(s):  
C.-G. Yu ◽  
R.L. Geiger
2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Maneesha Gupta ◽  
Richa Srivastava ◽  
Urvashi Singh

This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.


2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Panagiotis Samiotis ◽  
Costas Psychalinos

A novel complex filter topology realized using current feedback operational amplifiers as active elements is introduced in this paper. Offered benefits are the low-voltage operation capability and the requirement for employing only grounded passive elements. Two application examples are provided, where the frequency behavior of the derived filters fulfills the ZigBee and Bluetooth standards, respectively. Their performance evaluation has been done through simulation results at postlayout level, using MOS transistor models provided by AMS C35B4 CMOS process.


2013 ◽  
Vol 22 (08) ◽  
pp. 1350073 ◽  
Author(s):  
FABIAN KHATEB ◽  
NABHAN KHATIB ◽  
PIPAT PROMMEE ◽  
WINAI JAIKLA ◽  
LUKAS FUJCIK

This paper presents ultra-low voltage transconductor using a new bulk-driven quasi-floating-gate technique (BD-QFG). This technique leads to significant increase in the transconductance and the bandwidth values of the MOS transistor (MOST) under ultra-low voltage condition. The proposed CMOS structure of the transconductor is capable to work with ultra-low supply voltage of ±300 mV and low power consumption of 18 μW. The transconductance value of the transconductor is tunable by external resistor with wide linear range. To prove the validation of the new described technique a second-order Gm-C multifunction filter is presented as one of the possible applications. The simulation results using 0.18 μm CMOS N-Well process from TSMC show the attractive features of the proposed circuit.


2017 ◽  
Vol 24 (6) ◽  
pp. 2753-2764 ◽  
Author(s):  
G. S. Abarca-Jiménez ◽  
J. Mares-Carreño ◽  
M. A. Reyes-Barranca ◽  
B. Granados-Rojas ◽  
S. Mendoza-Acevedo ◽  
...  

2004 ◽  
Vol 830 ◽  
Author(s):  
P. Dimitrakis ◽  
P. Normand

ABSTRACTCurrent research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.


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