scholarly journals Surface micromachining of a micro electromechanical inertial transducer based on commercially available Floating Gate Transistor technology

2018 ◽  
Vol 31 (3) ◽  
pp. 48-51
Author(s):  
Griselda Stephany Abarca-Jiménez ◽  
Gabriel Romero-Paredes Rubio ◽  
Mario Alfredo Reyes-Barranca ◽  
Miguel Ángel Alemán-Arce ◽  
Jacobo Esteban Munguía-Cervantes ◽  
...  

This work presents the results of different surface micromachining processes done on a chip from On Semiconductor 0.5 µm commercially available CMOS technology. The intended objective is to fabricate a MEMS inertial transducer in a monolithic substrate, as the electronics for signal processing are based on a Floating Gate MOS transistor, fully integrated in the electromechanical structure. According to the available layers and design rules from the foundry, an inertial sensor chip was designed and fabricated, except the last post–processing step, i.e., the removal of the sacrificial layer and thus releasing the inertial structure based on a surface micromachining process, allowing the completed device to behave as designed.

Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).


2017 ◽  
Vol 24 (6) ◽  
pp. 2753-2764 ◽  
Author(s):  
G. S. Abarca-Jiménez ◽  
J. Mares-Carreño ◽  
M. A. Reyes-Barranca ◽  
B. Granados-Rojas ◽  
S. Mendoza-Acevedo ◽  
...  

Author(s):  
B. Granados-Rojas ◽  
M. A. Reyes-Barranca ◽  
Y. E. González-Navarro ◽  
G. S. Abarca-Jiménez ◽  
M. A. Alemán-Arce ◽  
...  

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.


Author(s):  
Tomotoshi Murakami ◽  
Nobumasa Hasegawa ◽  
Yoshiyuki Utagawa ◽  
Tomoyuki Arai ◽  
Shinji Yamaura

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