THAMON: Thermal-aware High-performance Application Mapping onto Opto-electrical network-on-chip

2021 ◽  
pp. 102315
Author(s):  
Meisam Abdollahi ◽  
Yasaman Firouzabadi ◽  
Fatemeh Dehghani ◽  
Siamak Mohammadi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Electrical Network ◽  
Application Mapping ◽  
On Chip ◽  
High Performance Application

scholarly journals Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

2021 ◽  
Author(s):  
Isiaka A. Alimi ◽  
Romil K. Patel ◽  
Oluyomi Aboderin ◽  
Abdelgader M. Abdalla ◽  
Ramoni A. Gbadamosi ◽  
...  
Keyword(s):  
High Performance ◽  
Research Direction ◽  
Network On Chip ◽  
Limiting Factor ◽  
Single Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Technology Advancement ◽  
On Chip ◽  
Heterogeneous Cores

Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE

2008 ◽  
Vol 18 (02) ◽  
pp. 239-255 ◽  
Author(s):  
JUN HO BAHN ◽  
SEUNG EUN LEE ◽  
YOON SEOK YANG ◽  
JUNGSOOK YANG ◽  
NADER BAGHERZADEH
Keyword(s):  
Low Power ◽  
High Performance ◽  
Programming Model ◽  
Current System ◽  
Future Generation ◽  
Network On Chip ◽  
System Level ◽  
Processor Array ◽  
Application Mapping ◽  
On Chip

As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to overcome such a limitation, the notion of utilizing Network-on-Chip (NoC) technologies for the future generation of high performance and low power chips for myriad of applications, in particular for wireless communication and multimedia processing, has been of great importance. In order for the NoC technologies to succeed, realistic specifications such as throughput, latency, moderate design complexity, programming model, and design tools are necessary requirements. For this purpose, we have covered some of the key and challenging design issues specific to the NoC architecture such as the router design, network interface (NI) issues, and complete system-level modeling. In this paper, we propose a multi-processor system platform adopting NoC techniques, called NePA (Network-based Processor Array). As a component of system platform, the fundamental NoC techniques including the router architecture and generic NI are defined and implemented adopting low power and clock efficient techniques. Using a high-level cycle-accurate simulation, various parameters relevant to its performance and its systematic modeling are extracted and analyzed. By combining various developed systematic models, we construct the tool chain to pursue hardware/software design tradeoffs necessary for better understanding of the NoC techniques. Finally utilizing implementation of parallel FFT algorithms on the homogeneous NePA, the feasibility and advantages of using NoC techniques are shown.

scholarly journals Self-Healing Router Approach for High-Performance Network-on-Chip

2021 ◽  
Vol 2 ◽  
pp. 485-496
Author(s):  
Kasem Khalil ◽  
Omar Eldash ◽  
Ashok Kumar ◽  
Magdy Bayoumi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Self Healing ◽  
On Chip

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

Integration ◽  
2021 ◽  
Author(s):  
Nizar Dahir ◽  
Ammar Karkar ◽  
Maurizio Palesi ◽  
Terrence Mak ◽  
Alex Yakovlev
Keyword(s):  
Power Density ◽  
Network On Chip ◽  
Multi Objective ◽  
Application Mapping ◽  
On Chip

scholarly journals Merging Plasmonics and Silicon Photonics Towards Greener and Faster “Network-on-Chip” Solutions for Data Centers and High-Performance Computing Systems

10.5772/51853 ◽  
2012 ◽  
Author(s):  
Sotirios Papaioannou ◽  
Konstantinos Vyrsokinos ◽  
Dimitrios Kalavrouziotis ◽  
Giannis Giannoulis ◽  
Dimitrios Apostolopoulos ◽  
...  
Keyword(s):  
High Performance Computing ◽  
Silicon Photonics ◽  
High Performance ◽  
Data Centers ◽  
Network On Chip ◽  
Computing Systems ◽  
On Chip ◽  
Performance Computing

Application Mapping on Network-on-Chip

2018 ◽  
pp. 119-154
Author(s):  
Santanu Kundu ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Application Mapping ◽  
On Chip

scholarly journals Six-port optical switch for cluster-mesh photonic network-on-chip

Nanophotonics ◽  
2018 ◽  
Vol 7 (5) ◽  
pp. 827-835 ◽  
Author(s):  
Hao Jia ◽  
Ting Zhou ◽  
Yunchou Zhao ◽  
Yuhao Xia ◽  
Jincheng Dai ◽  
...  
Keyword(s):  
High Performance ◽  
Optical Switching ◽  
Optical Switch ◽  
Optical Signal ◽  
Network On Chip ◽  
Transmission Experiment ◽  
Photonic Network ◽  
Benes Network ◽  
On Chip ◽  
Spectral Responses

AbstractPhotonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

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