Slicing of Si wafers through abrasive processes generates various surface defects on wafers such as cracks and surface contaminations. Also, the processes cause a significant material loss during slicing and subsequent polishing. Recently, efforts are being made to slice very thin wafers, and at the same time understand the thermal and microstructural damage caused due to sparking during wire-electrical discharge machining (wire-EDM). Wire-EDM has shown potential for slicing ultra-thin Si wafers of thickness < 200 μm. This work, therefore, presents an extensive experimental work on characterization of the thermal damage due to sparking during wire-EDM on ultra-thin wafers. The experiments were performed using Response surface methodology (RSM)-based central composite design (CCD). The damage was mainly characterized by scanning electron microscope (SEM), transmission electron microscopy (TEM), and Raman spectroscopy. The average thickness of thermal damage on the wafers was observed to be ∼16 μm. The damage was highly influenced by exposure time of wafer surface with EDM plasma spark. Also, with an increase in diameter of plasma spark, the surface roughness was found to increase. TEM micrographs have confirmed the formation of amorphous Si along with a region of fine grained Si entrapped inside the amorphous matrix. However, there were no signs of other defects like microcracks, twin boundaries, or fracture on the surfaces. Micro-Raman spectroscopy revealed that in order to slice a wafer with minimum residual stresses and very low presence of amorphous phases, it should be sliced at the lowest value of pulse on-time and at the highest value of open voltage (OV).
Multi Response Optimization of Wire Electrical Discharge Machining Process Parameters Using Taguchi based Grey Relational Analysis
