Delay-Locked Loops

2020 ◽  
pp. 346-367
Keyword(s):  
Delay Locked Loops

A New Error Correction Circuit for Delay Locked Loops

2013 ◽  
Vol 60 (6) ◽  
pp. 4387-4393 ◽  
Author(s):  
Pierre Maillard ◽  
W. Timothy Holman ◽  
T. Daniel Loveless ◽  
Lloyd W. Massengill
Keyword(s):  
Error Correction ◽  
Delay Locked Loops

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops

2019 ◽  
Vol 66 (10) ◽  
pp. 3775-3785 ◽  
Author(s):  
Alessio Santiccioli ◽  
Carlo Samori ◽  
Andrea L. Lacaita ◽  
Salvatore Levantino
Keyword(s):  
Modeling And Analysis ◽  
Delay Locked Loops

CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops

2001 ◽  
Vol 36 (3) ◽  
pp. 385-397 ◽  
Author(s):  
K. Iizuka ◽  
M. Miyamoto ◽  
Y. Ohta ◽  
T. Suyama ◽  
K. Hara ◽  
...  
Keyword(s):  
Matched Filters ◽  
Delay Locked Loops ◽  
Functional Blocks

PREDICTING THE JITTER OF PLL–DLL BASED FREQUENCY SYNTHESIZERS

2014 ◽  
Vol 12 (02) ◽  
pp. 1450016
Author(s):  
GOVIND S. PATEL ◽  
S. SHARMA
Keyword(s):  
Global Positioning System ◽  
Analog Circuits ◽  
Frequency Synthesizer ◽  
Phase Lock Loop ◽  
Frequency Synthesizers ◽  
Clock Generation ◽  
Step Procedure ◽  
Methodical Approach ◽  
Delay Locked Loops ◽  
Global Positioning

Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

Sign in / Sign up

Export Citation Format

Share Document