CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops

2001 ◽  
Vol 36 (3) ◽  
pp. 385-397 ◽  
Author(s):  
K. Iizuka ◽  
M. Miyamoto ◽  
Y. Ohta ◽  
T. Suyama ◽  
K. Hara ◽  
...  
2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.


2020 ◽  
Vol 96 (3s) ◽  
pp. 337-342
Author(s):  
И.И. Мухин ◽  
Р.С. Шабардин ◽  
Л.В. Недашковский ◽  
Д.Н. Морозов

В работе представлены результаты проектирования четырех микросхем квадратурных модуляторов и демодуляторов, в которых реализована коррекция динамических параметров цифровым способом, что достигается регулировкой режимов работы отдельных функциональных блоков схемы. Разработаны опытные образцы квадратурных модуляторов и демодуляторов на основе SiGe технологического процесса и приведены результаты измерений. Показано, что при регулировке изменение фазового разбаланса может достигать значений до 5°, амплитудный разбаланс - до 2,8 дБ, а подавление паразитных составляющих может быть больше 50 дБ. The paper presents four quadrature modulators and demodulators circuits design results. In these circuits the dynamic parameters are digitally corrected, which is achieved by adjusting the operation modes of separate functional blocks. Prototypes of quadrature modulators and demodulators manufactured on SiGe process were produced and the measurement results are presented. It is shown that during adjustment the change in phase imbalance can reach values up to 5 degrees, amplitude imbalance up to 2.8 dB, and suppression of spurious components can be more than 50 dB.


Author(s):  
A. G. Basden ◽  
L. Bardou ◽  
D. Bonaccini Calia ◽  
T. Buey ◽  
M. Centrone ◽  
...  

Author(s):  
Lei Cao ◽  
Guo-Ping Liu ◽  
Wenshan Hu ◽  
Jahan Zaib Bhatti

The Android-based networked control system laboratory (NCSLab) is a remote control laboratory that adopts an extensible architecture, mainly including Android mobile devices, MATLAB servers, controllers and test rigs. In order to conduct various simulations and experiments more effectively in NCSLab, the first key issue that needs to be solved is to enable users to design their own control algorithms or functional blocks on the Android client, rather than just using the basic block libraries provided by the system. So, this paper proposes and implements a scheme for Android-based compilation of C-MEX S-functions. With this new feature, users can design personalized algorithm according to their requirements in the form of S-functions, which can be called and executed after being compiled by MATLAB server. Finally, through the experiment validation of the three-degree-of-freedom air bearing spacecraft platform, it is proved that the method of Android-based C-MEX S-functions is reliable and efficient, and this scheme well enhances the functionality and mobility of Android-based NCSLab.


1977 ◽  
Vol 65 (5) ◽  
pp. 812-813
Author(s):  
K. Abend ◽  
A. Mattei
Keyword(s):  

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