scholarly journals High-efficiency D-TV energy harvesting system for low-input power

2016 ◽  
Vol 3 (1) ◽  
pp. 34-42 ◽  
Author(s):  
Tiago Moura ◽  
Nuno Borges de Carvalho ◽  
Pedro Pinho

In this work, a high-efficiency radio-frequency energy-harvesting system that takes use of the Portuguese Digital Television signal (750–758 MHz) to obtain DC power is proposed. To be useful, it is optimized to operate at low-power conditions. For the rectifier, three different solutions are presented: a single-series diode, a single-shunt diode, and a voltage-doubler configuration. The efficiency is similar for the three rectifiers – about 54% with a sine-wave excitation and −10.5 dBm of input power. Field measurements with the voltage-doubler have shown 63% efficiency for the same input power.

2013 ◽  
Vol 7 (15) ◽  
pp. 1254-1263 ◽  
Author(s):  
Diego Masotti ◽  
Alessandra Costanzo ◽  
Massimo Del Prete ◽  
Vittorio Rizzoli

2019 ◽  
Vol 28 (03) ◽  
pp. 1950048 ◽  
Author(s):  
Mohamed Mokhlès Mnif ◽  
Hassene Mnif ◽  
Mourad Loulou

The energy-harvesting radio frequency (RF) can be an attractive alternative energy capable of replacing all or some of the board batteries. The RF waves are present in several high frequencies ([Formula: see text] GHz) and at low power (a few [Formula: see text]W). An energy-harvesting circuit designed must provide 1[Formula: see text]V voltage at minimum that is able to operate an actuator or a sensor. The RF-DC rectifier is the main component of an energy-harvesting circuit. This paper presents a new design RF-DC rectifier circuit using the MOSFET transistors, the capacitors and the inductors. Our proposed circuit is a combination of an Inductor–Capacitor–Inductor–Capacitor (LCLC) serie-parallel resonant tank (SPRT) and rectifier cascade using the Dynamic threshold Voltage Cancellation (DVC) and the technique of the Internal threshold Voltage Cancellation (IVC). Our proposed circuit operates in dual frequencies [Formula: see text][Formula: see text]GHz and [Formula: see text][Formula: see text]GHz with a low input power [Formula: see text][Formula: see text][Formula: see text]W ([Formula: see text][Formula: see text]dbm) and [Formula: see text][Formula: see text][Formula: see text]W ([Formula: see text][Formula: see text]dbm), respectively. This circuit gives a Power Conversion Efficiency (PCE) of 56.9% and an output voltage [Formula: see text][Formula: see text]V for the frequency 2.543[Formula: see text]GHz and a PCE of 62.6% and an output voltage [Formula: see text][Formula: see text]V for the frequency 4[Formula: see text]GHz. The pre-layout simulations were performed using the Advanced Design System (ADS) and the technology used is CMOS 0.18[Formula: see text][Formula: see text]m from TSMC. The simulations were performed on the proposed circuit composed by three stages.


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