Ground fault analysis of low voltage DC micro-grids with active front-end converter

Author(s):  
M. Carminati ◽  
E. Ragaini ◽  
E. Tironi ◽  
S. Grillo ◽  
L. Piegari
1990 ◽  
Vol 137 (1) ◽  
pp. 57 ◽  
Author(s):  
M. Steyaert ◽  
Z. Chang
Keyword(s):  

Author(s):  
D. Yates ◽  
E. Lopez-Morillo ◽  
R. G. Carvajal ◽  
J. Ramirez-Angulo ◽  
E. Rodriguez-Villegas
Keyword(s):  

Author(s):  
Ram Gopal Sharma

Fault analysis study is the important parameter of economic, reliable and secure power system planning and operation. Power system studies are important during the planning and conceptual design stages of the project. This paper presents the fault analysis on IEEE-9 bus system. The line to ground fault is created on bus 5th and analyzed the variation in Voltage, Real power, Reactive power on different buses. The fault at 5th bus of IEEE-9 bus system is analyzed on PSCAD software.


2001 ◽  
Vol 37 (5) ◽  
pp. 1423-1437 ◽  
Author(s):  
G.L. Skibinski ◽  
B.M. Wood ◽  
J.J. Nichols ◽  
L.A. Barrios

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2060
Author(s):  
Na Bai ◽  
Liang Wang ◽  
Yaohua Xu ◽  
Yi Wang

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.


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